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H8/3002 Datasheet(PDF) 119 Page - Renesas Technology Corp |
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H8/3002 Datasheet(HTML) 119 Page - Renesas Technology Corp |
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119 / 700 page  6.1.2 Block Diagram Figure 6-1 shows a block diagram of the bus controller. Figure 6-1 Block Diagram of Bus Controller 0 CS to 3 CS ABWCR ASTCR WCER WCR BRCR BACK BREQ WAIT Internal address bus Area decoder Bus control circuit Wait-state controller Bus arbiter Bus mode control signal Bus size control signal Access state control signal Wait request signal CPU bus request signal DMAC bus request signal Refresh controller bus request signal CPU bus acknowledge signal DMAC bus acknowledge signal Refresh controller bus acknowledge signal Legend ABWCR: ASTCR: WCER: WCR: BRCR: Bus width control register Access state control register Wait state controller enable register Wait control register Bus release control register Internal signals Internal signals 104 |
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