H8SLASH3002 datasheet(311/700 Pages) RENESAS

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Bit 1—Buffer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or

whether GRB3 is buffered by BRB3.

Bit 1

BFB3

Description

GRB3 operates normally

(Initial value)

GRB3 is buffered by BRB3

Bit 0—Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or

whether GRA3 is buffered by BRA3.

Bit 0

BFA3

Description

GRA3 operates normally

(Initial value)

GRA3 is buffered by BRA3

10.2.5 Timer Output Master Enable Register (TOER)

TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3

and 4.

TOER is initialized to H'FF by a reset and in standby mode.

Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 1.

Bit

Initial value

Read/Write

—

EXB4

R/W

EXA4

R/W

EB3

R/W

EA3

R/W

EB4

R/W

EA4

R/W

Reserved bits

Master enable TOCXA4, TOCXB4

These bits enable or disable output

settings for pins TOCXA4and TOCXB4

Master enable TIOCA3, TIOCB3 , TIOCA4, TIOCB4

These bits enable or disable output settings for pins

TIOCA3, TIOCB3 , TIOCA4, and TIOCB4

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H8/3002 Datasheet(PDF) 311 Page - Renesas Technology Corp

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