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H8/3002 Datasheet(PDF) 327 Page - Renesas Technology Corp |
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H8/3002 Datasheet(HTML) 327 Page - Renesas Technology Corp |
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327 / 700 page  10.3 CPU Interface 10.3.1 16-Bit Accessible Registers The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a word at a time, or a byte at a time. Figures 10-6 and 10-7 show examples of word access to a timer counter (TCNT). Figures 10-8, 10-9, 10-10, and 10-11 show examples of byte access to TCNTH and TCNTL. Figure 10-6 Access to Timer Counter (CPU Writes to TCNT, Word) Figure 10-7 Access to Timer Counter (CPU Reads TCNT, Word) On-chip data bus CPU H L Bus interface H L Module data bus TCNTH TCNTL On-chip data bus CPU H L Bus interface H L Module data bus TCNTH TCNTL 313 |
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