M38K09RFS datasheet(84/328 Pages) RENESAS

84 / 328 page

FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 05, 2006

page 67 of 112

38K0 Group

REJ09B0337-0200

HARDWARE

Dack =

“0”

Dack =

“0”

Dack =

“0”

Mch_req

012

req

010016

010116

010216

010316

ack

DMA acknowledge

ExDACK

mWR

detection

mWR

detection

DMA request

ExDREQ

➀

➁

➁’

➂➃

➄

➂➃

➄

Address ExA0

Chip select ExCS

Read ExRD

Write ExWR

Data DQ0 to DQ7

Internal clock

Operation enabled

Main sequencer

Internal memory access

Acknowledgment of

internal memory access

Memory address

Counter end

Burst end

Memory channel operation

end interrupt

A0 = “x”

CS = “1”

A0 = “x”

CS = “1”

A0 = “x”

CS = “1”

External I/O configuration register

Set as necessary.

Memory channel operation mode register

MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)

Burst (burst) = “1” (Burst mode)

Memory address counter

(Example) 010016

End address register

(Example) 010216

EXB interrupt source enable register

MC_ENB (Memory channel operation enable) = “1” (Operation start)

➀ In the memory channel receive mode when the command for enabling operation is written, assertion of the memory channel request which synchronized

with a rise of

φ is made.

➁ When a rise of ExWR is detected, an internal memory access sequence which synchronized with a rise of φ is activated and a data is written in the internal

memory within two clocks at a minimum.

➂ The memory address counter is increased simultaneously at the former data write completion.

➃ When the memory address counter reaches the end address, the detection circuit of external write signal (ExWR) operation is enabled and negation of the

memory channel request which synchronized with the following

φ is made.

➄ When the write operation to the end address has been completed, the memory address counter is increased and the memory channel operation end

interrupt is generated.

Receive buffer RXBUF

(4) Memory Channel Receiving Operation (2)-

Burst Mode

Memory channel receiving operation (2) is shown bellow.

Fig. 95 Memory channel receiving operation (2)

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