M38K09RFS datasheet(12/328 Pages) RENESAS

12 / 328 page

Rev.2.00

Oct 05, 2006

page 8 of 13

38K0 Group

REJ09B0337-0200

Fig. 2.4.6 Structure of Baud rate generator ................................................................................ 43

Fig. 2.4.7 Structure of Interrupt edge selection register ........................................................... 43

Fig. 2.4.8 Structure of Interrupt request register 2 .................................................................... 44

Fig. 2.4.9 Structure of Interrupt control register 2 ..................................................................... 44

Fig. 2.4.10 Serial I/O connection examples (1) .......................................................................... 45

Fig. 2.4.11 Serial I/O connection examples (2) .......................................................................... 46

Fig. 2.4.12 Serial I/O transfer data format .................................................................................. 47

Fig. 2.4.13 Connection diagram .................................................................................................... 48

Fig. 2.4.14 Timing chart ................................................................................................................. 48

Fig. 2.4.15 Registers setting related to transmitting side ......................................................... 49

Fig. 2.4.16 Registers setting related to receiving side .............................................................. 50

Fig. 2.4.17 Control procedure of transmitting side ..................................................................... 51

Fig. 2.4.18 Control procedure of receiving side ......................................................................... 52

Fig. 2.4.19 Connection diagram .................................................................................................... 53

Fig. 2.4.20 Timing chart ................................................................................................................. 53

Fig. 2.4.22 Setting of serial I/O transmission data .................................................................... 54

Fig. 2.4.21 Registers setting related to Serial I/O ..................................................................... 54

Fig. 2.4.23 Control procedure of Serial I/O ................................................................................. 55

Fig. 2.4.24 Connection diagram .................................................................................................... 56

Fig. 2.4.25 Timing chart ................................................................................................................. 57

Fig. 2.4.26 Related registers setting ............................................................................................ 57

Fig. 2.4.27 Control procedure of master unit .............................................................................. 58

Fig. 2.4.28 Control procedure of slave unit ................................................................................ 59

Fig. 2.4.29 Connection diagram (Communication using UART) ............................................... 60

Fig. 2.4.30 Timing chart (using UART) ........................................................................................ 60

Fig. 2.4.31 Registers setting related to transmitting side ......................................................... 62

Fig. 2.4.32 Registers setting related to receiving side .............................................................. 63

Fig. 2.4.33 Control procedure of transmitting side ..................................................................... 64

Fig. 2.4.34 Control procedure of receiving side ......................................................................... 65

Fig. 2.4.35 Sequence of setting serial I/O control register again ............................................ 67

Fig. 2.7.1 Memory map of registers related to A/D converter .................................................. 71

Fig. 2.7.2 Structure of AD control register .................................................................................. 71

Fig. 2.7.3 Structure of AD conversion register 1 ....................................................................... 72

Fig. 2.7.4 Structure of AD conversion register 2 ....................................................................... 72

Fig. 2.7.5 Structure of Interrupt request register 2 .................................................................... 73

Fig. 2.7.6 Structure of Interrupt control register 2 ..................................................................... 73

Fig. 2.7.7 Connection diagram ...................................................................................................... 74

Fig. 2.7.8 Related registers setting .............................................................................................. 74

Fig. 2.7.9 Control procedure for 8-bit read ................................................................................. 75

Fig. 2.7.10 Control procedure for 10-bit read ............................................................................. 75

Fig. 2.8.1 Memory map of registers related to watchdog timer ............................................... 77

Fig. 2.8.2 Structure of Watchdog timer control register ............................................................ 77

Fig. 2.8.3 Structure of CPU mode register ................................................................................. 78

Fig. 2.8.4 Watchdog timer connection and division ratio setting ............................................. 79

Fig. 2.8.5 Related registers setting .............................................................................................. 80

Fig. 2.8.6 Control procedure .......................................................................................................... 80

Fig. 2.9.1 Example of poweron reset circuit ............................................................................... 81

Fig. 2.9.2 RAM backup system ..................................................................................................... 81

Fig. 2.10.1 Memory map of registers related to PLL ................................................................. 83

Fig. 2.10.2 Structure of USB control register ............................................................................. 83

Fig. 2.10.3 Structure of CPU mode register ............................................................................... 84

Fig. 2.10.4 Structure of PLL control register .............................................................................. 84

List of figures

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