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M38K09RFS Datasheet(PDF) 88 Page - Renesas Technology Corp |
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M38K09RFS Datasheet(HTML) 88 Page - Renesas Technology Corp |
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88 / 328 page  FUNCTIONAL DESCRIPTION Rev.2.00 Oct 05, 2006 page 71 of 112 38K0 Group REJ09B0337-0200 HARDWARE MULTICHANNEL RAM The 38K0 group has the built-in multichannel RAM including the small logic circuit (RAM I/F) instead of ordinary RAM. The multichannel RAM has the USB channel and the EXB channel in addition to the CPU channel. The multichannel RAM controls access from CPU, USB and EXB, synchronizing control with φ. The USB transfer rate is about 1.5 Mbytes/second. Access to the multichannel RAM is performed at every about 5.3 clocks in φ = 8 MHz, or at every about 4 clocks in φ = 6 MHz. The USB’s access has priority to the EXB’s. The one wait function (ONW function) of 38000 series CPU is used internally to control access with the CPU. When receiving an access request from the USB or the EXB, the multichannel RAM outputs ONW signal to wait the CPU for one clock, and access of the USB or the EXB is performed. If the multichannel RAM is outputting ONW signal while the CPU is in the state of reading/writing for the RAM area, the CPU read cycle or write cycle is extended by 1 period of φ. Fig. 99 Multichannel RAM timing diagram (no wait) φ CPU AD RD/WR USB REQ EXB REQ ONW RAM access right RAM RD/WR CPU bus cycle Multichannel RAM RAM bus cycle CPU USB CPU RAM area Except RAM RAM area No wait No wait No wait Except RAM No RD/WR φ CPU AD RD/WR USB REQ EXB REQ ONW RAM access right RAM RD/WR One wait 2-cycle wait (max.) for EXB Prior CPU Prior CPU Prior USB RAM area One wait USB having priority of USB/EXB simultaneous access Prior CPU RAM area CPU CPU CPU EXB CPU USB USB RAM area EXB Multichannel RAM RAM bus cycle CPU bus cycle One wait Prohibiting continuous access of USB/EXB CPU accessing RAM at the latter part One wait RAM area Fig. 100 Multichannel RAM timing diagram (one wait) ONW = “H” |
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