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M38K09RFS Datasheet(PDF) 106 Page - Renesas Technology Corp

Part # M38K09RFS
Description  RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
PDF  328 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M38K09RFS Datasheet(HTML) 106 Page - Renesas Technology Corp

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FUNCTIONAL DESCRIPTION
Rev.2.00
Oct 05, 2006
page 89 of 112
38K0 Group
REJ09B0337-0200
HARDWARE
Table 10 Definition of each bit in status register
Status Register (SRD)
The status register shows the operating status of the flash
memory and whether erase operations and programs ended suc-
cessfully or in error. It can be read in the following ways:
(1) By reading an arbitrary address from the User ROM area after
writing the read status register command (7016)
(2) By reading an arbitrary address from the User ROM area in the
period from when the program starts or erase operation starts
to when the read array command (FF16) is input.
Also, the status register can be cleared by writing the clear status
register command (5016).
After reset, the status register is set to “8016”.
Table 10 shows the status register. Each bit in this register is ex-
plained below.
•Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. This bit is set to “0” (busy) during write or erase operation
and is set to “1” when these operations ends.
After power-on, the sequencer status is set to “1” (ready).
•Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
•Program status (SR4)
The program status indicates the operating status of write opera-
tion. When a write error occurs, it is set to “1”.
The program status is set to “0” when it is cleared.
If “1” is written for any of the SR5 and SR4 bits, the program,
erase all blocks, and block erase commands are not accepted.
Before executing these commands, execute the clear status regis-
ter command (5016) and clear the status register.
Each bit of
SRD0 bits
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Definition
“1”
“0”
Sequencer status
Reserved
Erase status
Program status
Reserved
Reserved
Reserved
Reserved
Ready
-
Terminated in error
Terminated in error
-
-
-
-
Status name
Busy
-
Terminated normally
Terminated normally
-
-
-
-



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