M38K09RFS datasheet(140/328 Pages) RENESAS

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2.2 Interrupt

Rev.2.00

Oct 05, 2006

page 11 of 111

38K0 Group

REJ09B0337-0200

APPLICATION

2.2.3 Interrupt source

The 38K0 group permits interrupts of 15 sources. These are vector interrupts with a fixed priority system.

Accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority

interrupt is accepted first. This priority is determined by hardware, but a variety of priority processing can

be performed by software, using an interrupt enable bit and an interrupt disable flag.

For interrupt sources, vector addresses and interrupt priority, refer to Table 2.2.1.

Table 2.2.1 Interrupt sources, vector addresses and priority of 38K0 group

Remarks

Low

FFFC16

FFFA16

FFF816

FFF616

FFF416

FFF216

FFF016

FFEE16

FFEC16

FFEA16

FFE816

FFE616

FFE416

FFE216

FFE016

FFDE16

FFDC16

High

FFFD16

FFFB16

FFF916

FFF716

FFF516

FFF316

FFF116

FFEF16

FFED16

FFEB16

FFE916

FFE716

FFE516

FFE316

FFE116

FFDF16

FFDD16

Notes 1: Vector addresses contain interrupt jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

3: Nothing is arranged in these vector addresses.

4: Fix bit 1 of interrupt control register 2 (address 003F16) to “0”.

Vector Addresses (Note 1)

Non-maskable

Valid when USB mode

Valid when external bus is selected

External interrupt

(active edge selectable)

STP release timer underflow

External interrupt

(active edge selectable)

(Note 4)

Valid when serial I/O is selected

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

Non-maskable software interrupt

Interrupt Source

Reset (Note 2)

USB bus reset

USB SOF

USB device

External bus

INT0

Timer X

Timer 1

Timer 2

INT1

(Note 3)

Serial I/O

reception

Serial I/O

transmission

CNTR0

Key-on wake up

A/D conversion

BRK instruction

Priority

—

Interrupt Request

Generating Conditions

At reset

At detection of USB bus reset

signal (2.5

µs interval SE0)

At detection of USB SOF signal

At detection of resume signal (K

state or SE0) or suspend signal

(3 ms interval bus idle), or at

completion of transaction

At completion of reception or

transmission or at completion of

DMA transmission

At detection of either rising or

falling edge of INT0 input

At timer X underflow

At timer 1 underflow

At timer 2 underflow

At detection of either rising or

falling edge of INT1 input

(Note 4)

At completion of serial I/O data

reception

At completion of serial I/O data

transmission

At detection of either rising or

falling edge of CNTR0 input

At falling of conjunction of input

level for port P0 (at input mode)

At completion of A/D conversion

At BRK instruction execution

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