M38K09RFS datasheet(164/328 Pages) RENESAS

164 / 328 page

2.3 Timer

Rev.2.00

Oct 05, 2006

page 35 of 111

38K0 Group

REJ09B0337-0200

APPLICATION

Fig. 2.3.19 Control procedure

RESET

IREQ1(address 3C16), bit5 ?

RTI

← TX (address 2516)

214 < (A) < 228

Fpulse

← 0

q x: This bit is not used here. Set it to “0” or “1” arbitrary.

•All interrupts disabled

•Timer X operating mode : Event counter mode

(Count a falling edge of pulses input from CNTR0 pin.)

•Division ratio set so that Timer 1 interrupt will occur at

2 ms intervals.

•Timer X count start

•Interrupts enabled

Note 1: When using Index X mode flag (T)

Note 2: When using Decimal mode flag (D)

•Push registers used in interrupt process routine

•Pop registers pushed to stack

•Counter value initialized

•Timer X interrupt request bit cleared

Initialization

•Timer 1 interrupt enabled

Timer 1 interrupt process routine

CLT (Note 1)

CLD (Note 2)

Push registers to stack

•Processing as out of range when the count value is 256 or more

•Count value read

•Count value into Accumulator (A) stored

In range

Out of range

•Read value with reference value

compared

•Comparison result to flag Fpulse

stored

Process judgment result

Pop registers

SEI

(address 2316)

← XXXX11102

PRE12

(address 2016)

← 3 – 1

(address 2116)

← 250 – 1

PREX

(address 2416)

← 1 – 1

(address 2516)

← 256 – 1

ICON1

(address 3E16), bit6

← 1

(address 2316), bit3

← 0

CLI

Fpulse

← 1

(address 2516)

← 256 – 1

IREQ1

(address 3C16), bit5

← 0

(A)

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