M38K09RFS datasheet(274/328 Pages) RENESAS

274 / 328 page

3.3 Countermeasures against noise

Rev.2.00

Oct 05, 2006

page 33 of 89

38K0 Group

REJ09B0337-0200

APPENDIX

Noise

CNVSS

VSS

CNVSS

VSS

N.G.

O.K.

(3)

Wiring for clock input/output pins

• Make the length of wiring which is connected to clock I/O pins as short as possible.

• Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is

connected to an oscillator and the VSS pin of a microcomputer as short as possible.

• Separate the VSS pattern only for oscillation from other VSS patterns.

q Reason

If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program

failure or program runaway. Also, if a potential difference is caused by the noise between the VSS

level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in

the microcomputer.

Fig. 3.3.3 Wiring for clock I/O pins

(4)

Wiring to CNVSS pin

Connect the CNVSS pin to the VSS pin with the shortest possible wiring.

q Reason

The processor mode of a microcomputer is influenced by a potential at the CNVSS pin. If a

potential difference is caused by the noise between pins CNVSS and VSS, the processor mode may

become unstable. This may cause a microcomputer malfunction or a program runaway.

Fig. 3.3.4 Wiring for CNVSS pin

Noise

XIN

XOUT

VSS

XIN

XOUT

VSS

N.G.

O.K.

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