UPSD3233 datasheet(35/170 Pages) STMICROELECTRONICS

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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

INTERRUPT SYSTEM

There are interrupt requests from 10 sources as

follows.

■

INT0 external interrupt

■

2nd USART Interrupt

■

Timer 0 Interrupt

■

I2C Interrupt

■

INT1 External Interrupt (or ADC Interrupt)

■

DDC Interrupt

■

Timer 1 Interrupt

■

USB Interrupt

■

USART Interrupt

■

Timer 2 Interrupt

External Int0

–

The INT0 can be either level-active or

transition-active depending on Bit IT0 in

generates this interrupt is Bit IE0 in TCON.

–

When an external interrupt is generated, the

corresponding request flag is cleared by the

hardware when the service routine is vectored

to only if the interrupt was transition activated.

–

If the interrupt was level activated then the

interrupt request flag remains set until the

requested interrupt is actually generated.

Then it has to deactivate the request before

the interrupt service routine is completed, or

else another interrupt will be generated.

Timer 0 and 1 Interrupts

–

Timer 0 and Timer 1 Interrupts are generated

by TF0 and TF1 which are set by an overflow

of their respective Timer/Counter registers

(except for Timer 0 in Mode 3).

–

These flags are cleared by the internal

hardware when the interrupt is serviced.

Timer 2 Interrupt

–

Timer 2 Interrupt is generated by TF2 which is

set by an overflow of Timer 2. This flag has to

be cleared by the software - not by hardware.

–

It is also generated by the T2EX signal (Timer

2 External Interrupt P1.1) which is controlled

by EXEN2 and EXF2 Bits in the T2CON

I2C Interrupt

–

The interrupt of the I2C is generated by Bit

INTR in the register S2STA.

–

This flag is cleared by hardware.

External Int1

–

The INT1 can be either level active or

transition active depending on Bit IT1 in

generates this interrupt is Bit IE1 in TCON.

–

When an external interrupt is generated, the

corresponding request flag is cleared by the

hardware when the service routine is vectored

to only if the interrupt was transition activated.

–

If the interrupt was level activated then the

interrupt request flag remains set until the

requested interrupt is actually generated.

Then it has to deactivate the request before

the interrupt service routine is completed, or

else another interrupt will be generated.

–

The ADC can take over the External INT1 to

generate an interrupt on conversion being

completed

DDC Interrupt

–

The DDC Interrupt is generated either by Bit

INTR in the S1STA register for DC2B protocol

or by Bit DDC Interrupt in the DDCCON

Bit in the DDCCON register when DDC

protocol is changed from DDC1 to DDC2.

–

Flags except the INTR have to be cleared by

the software. INTR flag is cleared by

hardware.

USB Interrupt

–

The USB Interrupt is generated when

endpoint0 has transmitted a packet or

received a packet, when endpoint1 or

endpoint2 has transmitted a packet, when the

suspend or resume state is detected and

every EOP received.

–

When the USB Interrupt is generated, the

corresponding request flag must be cleared by

software. The interrupt service routine will

have to check the various USB registers to

determine the source and clear the

corresponding flag.

–

Please see the dedicated interrupt control

registers for the USB peripheral for more

information.

UPSD3233 Datasheet(PDF) 35 Page - STMicroelectronics

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