UPSD3233 datasheet(45/170 Pages) STMICROELECTRONICS

45 / 170 page

45/170

uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

OSCILLATOR

The oscillator circuit of the uPSD323X Devices is

a single stage inverting amplifier in a Pierce oscil-

lator configuration. The circuitry between XTAL1

and XTAL2 is basically an inverter biased to the

transfer point. Either a crystal or ceramic resonator

can be used as the feedback element to complete

the oscillator circuit. Both are operated in parallel

resonance.

XTAL1 is the high gain amplifier input, and XTAL2

is the output. To drive the uPSD323X Devices ex-

ternally, XTAL1 is driven from an external source

and XTAL2 left open-circuit.

Figure 19. Oscillator

SUPERVISORY

There are four ways to invoke a reset and initialize

the uPSD323X Devices.

■

Via the external RESET pin

■

Via the internal LVR Block.

■

Via USB bus reset signaling.

■

Via Watch Dog timer

The RESET mechanism is illustrated in Figure 20.

Each RESET source will cause an internal reset

signal active. The CPU responds by executing an

internal reset and puts the internal registers in a

defined state. This internal reset is also routed as

an active low reset input to the PSD Module.

Figure 20. RESET Configuration

AI06620

XTAL1

XTAL2

8 to 40 MHz

XTAL1

XTAL2

External Clock

AI06621

Reset

CPU

PERI.

Noise

Cancel

LVR

CPU

Clock

Sync

10ms

Timer

USB Reset

RSTE

WDT

PSD_RST

“Active Low

10ms at 40Mhz

50ms at

8Mhz

UPSD3233 Datasheet(PDF) 45 Page - STMicroelectronics

UPSD3233 Datasheet(HTML) 45 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL