UPSD3233 datasheet(40/170 Pages) STMICROELECTRONICS

40 / 170 page

uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

40/170

POWER-SAVING MODE

Two software selectable modes of reduced power

consumption are implemented.

Idle Mode

The following Functions are Switched Off.

■

CPU (Halted)

The following Function Remain Active During Idle

Mode.

■

External Interrupts

■

Timer 0, Timer 1, Timer 2

■

DDC Interface

■

PWM Units

■

USB Interface

■

USART

■

8-bit ADC

■

I2C Interface

Note: Interrupt or RESET terminates the Idle

Mode.

Power-Down Mode

■

System Clock Halted

■

LVD Logic Remains Active

■

SRAM contents remains unchanged

■

The SFRs retain their value until a RESET is

asserted

Note: The only way to exit Power-down Mode is a

RESET.

Table 25. Power-Saving Mode Power Consumption

Power Control Register

The Idle and Power-down Modes are activated by software via the PCON register.

Table 26. Pin Status During Idle and Power-down Mode

Table 27. Description of the PCON Bits

Note: 1. See the T2CON register for details of the flag description

Mode

Addr/Data

Ports1,3,4

PWM

I2C

DDC

USB

Idle

Maintain Data

Active

Power-down

Maintain Data

Disable

SFR

Addr

Reg

Name

Bit Register Name

Reset

Value

Comments

PCON

SMOD

SMOD1

LVREN ADSFINT RCLK1

TCLK1

IDLE

Power Ctrl

Bit

Symbol

Function

SMOD

Double baud data rate bit UART

SMOD1

Double baud data rate bit 2nd UART

LVREN

LVR disable bit (active High)

ADSFINT

Enable ADC Interrupt

RCLK1(1)

Received clock flag (UART 2)

TCLK1(1)

Transmit clock flag (UART 2)

Activate Power-down Mode (High enable)

IDL

Activate Idle Mode (High enable)

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