OMAP3530-HiRel datasheet(116/239 Pages) TI

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OMAP

DLL

vdds_dpll_dll

PowerRail

DPLL4

DPLL1

DPLL2

DPLL3

vdds_dpll_per

DPLL5

030-016

4.3.1

Digital Phase-Locked Loop (DPLL)

4.3.1.1 DPLL1 (MPU)

4.3.1.2 DPLL2 (IVA2)

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

SPRS599 – JUNE 2009

www.ti.com

Figure 4-10. DPLL and DLL Implementation

For more information on the OMAP3525 and OMAP3530 Applications Processors DPLLs and clocking

structure, see the Power, Reset, and Clock management (PRCM) chapter of the OMAP35x Applications

Processor TRM (literature number SPRUFA5).

The DPLL provides all interface clocks and some functional clocks (such as the processor clocks) of the

OMAP3525 and OMAP3530 devices.

DPLL1 and DPLL2 get an always-on clock used to produce the synthesized clock. They get a high-speed

bypass clock used to switch the DPLL output clock on this high-speed clock during bypass mode.

The high-speed bypass clock is an L3 divided clock (programmable by 1 or 2) that saves DPLL processor

power consumption when the processor does not need to run faster than the L3 clock speed, or optimizes

performance during frequency scaling.

Each DPLL synthesized frequency is set by programming M (multiplier) and N (divider) factors. In addition,

all DPLL outputs can be controlled by an independent divider (M2 to M6).

The clock generating DPLLs of the OMAP3525 and OMAP3530 devices have following features:

• Independent power domain per DPLL

• Controlled by clock-manager (CM)

• Fed with always-on system clock with independent gating control per DPLL

• Analog part supplied through dedicated power supply (1.8 V) and an embedded LDO to get rid of

1-MHz noise

• Up to five independent output dividers for simultaneous generation of multiple clock frequencies

DPLL1 is located in the MPU subsystem and supplies all clocks of the subsystem. All MPU subsystem

clocks are internally generated in the subsystem. When the core domain is on, it can use the DPLL3

(CORE DPLL) output as a high-frequency bypass input clock.

DPLL2 is located in the IVA subsystem and supplies all clocks of the subsystem. All IVA subsystem clocks

are internally generated in the subsystem. When the core domain is on, it can use the DPLL3 (CORE

DPLL) output as a high-frequency bypass input clock.

CLOCK SPECIFICATIONS

116

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