 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
OMAP3530-HiRel Datasheet(PDF) 119 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
OMAP3530-HiRel Datasheet(HTML) 119 Page - Texas Instruments |
|
|
119 / 239 page  OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 – JUNE 2009 Table 4-15. DPLL1 Clock Frequency Ranges Clock Signal Description Max Unit OPP5 600 MHz OPP4 550 MHz ARM_CLK DPLL1 output clock. OPP3 500 MHz OPP2 250 MHz OPP1 125 MHz Table 4-16. DPLL2 Clock Frequency Ranges Clock Signal Description Max Unit OPP5 430 MHz OPP4 400 MHz Generated from DPLL2 output IVA2_CLK OPP3 360 MHz clock. OPP2 180 MHz OPP1 90 MHz Table 4-17 through Table 4-19 show the DPLL3 clock frequency ranges. Note: The DPLL3 clock frequency ranges depend on the VDD2 (vdd_core) operating point and the L3 clock speed configuration. Table 4-17. DPLL3 Clock Frequency Ranges, VDD2 OPP3 Config 1 Config 2 Config 3 (166 MHz) (133 MHz) (100 MHz) Unit Clock Signal Description Min Max Min Max Min Max Output of clock manager (CM), CM: CORE_CLK - 332 - 266 - 200 MHz generated directly from DPLL3. Output of clock manager (CM), CM: L3_ICLK - 166 - 133 - 100 MHz generated using DPLL3. Output of clock manager (CM), CM: L4_ICLK generated using CM L3_ICLK and - 83 - 66.5 - 50 MHz divider. SGX input clock, taken from CM SGX - 110.67 - 88.67 - 66.67 MHz CORE_CLK. SDRC input clock, taken from CM SDRC - 166 - 133 - 100 MHz L3_ICLK. GPMC input clock, taken from CM GPMC - 83 - 66.5 - 100 MHz L3_ICLK. Table 4-18. DPLL3 Clock Frequency Ranges, VDD2 OPP2 Config 1 Config 2 (83 MHz) (100 MHz) Unit Clock Signal Description Min Max Min Max Output of clock manager (CM), generated CM: CORE_CLK - 166 - 200 MHz directly from DPLL3. Output of clock manager (CM), generated using CM: L3_ICLK - 83 - 100 MHz DPLL3. Output of clock manager (CM), generated using CM: L4_ICLK - 41.5 - 50 MHz CM L3_ICLK and divider. SGX SGX input clock, taken from CM CORE_CLK. - 55.53 - 66.67 MHz SDRC SDRC input clock, taken from CM L3_ICLK. - 83 - 100 MHz GPMC GPMC input clock, taken from CM L3_ICLK. - 83 - 50 MHz Submit Documentation Feedback CLOCK SPECIFICATIONS 119 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
