TMC2193 datasheet(49/72 Pages) CADEKA

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PRODUCT SPECIFICATION

TMC2193

REV. 1.0 3/26/03

Control Register Deﬁnitions (continued)

Vertical Blanking Interval Enable Register (0x19)

76543210

SHORT

T512

HALFEN

VBIENF2

Reg

Bit

Name

Description

SHORT

Test Register. Program LOW.

T512

EH/SL Offset Control Bit.

When LOW, the true value of EH and SL is offset by 256.

When HIGH, the true value of EH and SL is offset by 512.

HALFEN

Half Line Enable.

When LOW, half-line blanking occurs on line 283 (NTSC) or line 23 (PAL).

When HIGH, line 283 (NTSC) or line 23 (PAL) is treated as a full line of

active video.

4-0

VBIENF2

VBI Active Video Enable, Field 2.

The value of VBIENF2 determines which line blanking stops and active line

for ODD fields in NTSC starting from line 4 to line 35 or an EVEN fields for

PAL starting from line 1 to line 32.

Pedestal Height Register (0x1A)

76543210

Reserved

PEDHGT1

Reg

Bit

Name

Description

Reserved

6-0

PEDHGT1

Composite Pedestal Height.

PEDHGT1 is a 2’s comp value producing a pedestal height from -22.1 IRE

to 21.7 IRE with .345 IRE steps on the composite data path. The default 7.5

IRE pedestal for NTSC-M results from a hex code of 0010110b.

Closed Caption Register (0x1C)

76543210

CCD1

Reg

Bit

Name

Description

7-0

CCD1

First Byte of CC Data.

Bit 0 is the LSB. The MSB will be overwritten by an ODD Parity Bit if

CCPAR is HIGH.

TMC2193 Datasheet(PDF) 49 Page - Cadeka Microcircuits LLC.

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