TMC2193 datasheet(40/72 Pages) CADEKA

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TMC2193

PRODUCT SPECIFICATION

REV. 1.0 3/26/03

Control Register Deﬁnitions (continued)

General Control Register (0x06)

76543210

FORMAT

MODE

PDCDIR

TOUT

TSOUT

Reg

Bit

Name

Description

7-6

FORMAT

Video Format.

NTSC

PAL – B,G,H,I,N

PAL – M

Reserved

5-3

MODE

Video Mode.

000

MASTER with free-running subcarrier

001

SLAVE with free-running subcarrier

010

CCIR656 with free-running subcarrier

011

GENLOCK with subcarrier phase and frequency locked to the GRS

information.

100

MASTER with subcarrier phase reset every 8 fields

101

SLAVE with subcarrier phase reset every 8 fields

110

CCIR656 with subcarrier phase reset every 8 fields.

111

DRS-Lock with subcarrier phase and frequency locked to the DRS

information.

PDCDIR

PDC Directional Control.

When PDC is LOW, the PDC pin is an output.

When PDCDIR is HIGH, the PDC pin is an input that can override the

internally generated PDC and blank the active video of a line.

TOUT

External Sync Output Control.

When TOUT = LOW, a MPEG style field toggle is the output on pin VSOUT.

When TOUT = HIGH, a traditional vertical sync is the output on pin VSOUT.

TSOUT

External Sync Delay Control.

When the TSOUT is LOW, HSOUT, VSOUT are delayed to match

propagation delay through the chip. When TSOUT is HIGH, HSOUT,

VSOUT are aligned with the incoming data on the PD port.

TMC2193 Datasheet(PDF) 40 Page - Cadeka Microcircuits LLC.

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