TMC2193 datasheet(64/72 Pages) CADEKA

64 / 72 page

TMC2193

PRODUCT SPECIFICATION

REV. 1.0 3/26/03

Electrical Characteristics

Notes:

1. Typical IDD with VDD = +5.0 Volts and TA = 25

°C.

2. Timing reference points are at the 50% level.

Switching Characteristics

Notes:

1. Timing reference points are at the 50% level.

2. Analog CLOAD <10 pF, D7-0 load <40 pF.

3. Pipeline delay, with respect to PXCK, is a function of the phase relationship between the internally generated PCK (PXCK/2)

and PXCK, as established by the hardware RESET.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

IDD

Power Supply Current

VDD = Max., fPXCK = 27MHz

335

375

IDDQ

Power Supply Current

(D/A disabled)

VDD = Max., fPXCK = 27MHz

VRO

Voltage Reference Output

1.235

IBR

Input Bias Current, VREF

VREF = Nom.

µA

IIH

Input Current, Logic HIGH

VDD = Max., VIN = VDD

µA

IIL

Input Current, Logic LOW

VDD = Max., VIN = GND

-10

µA

VOH

Output Voltage, Logic HIGH

IOH = Max.

2.4

VOL

Output Voltage, Logic LOW

IOL = Max.

0.4

IOZH

Hi-Z Leakage current, HIGH

VDD = Max., VIN = VDD

µA

IOZL

Hi-Z Leakage current, LOW

VDD = Max., VIN = GND

-10

µA

Digital Input Capacitance

TA = 25

°C, f = 1MHz

Digital Output Capacitance

TA = 25

°C, f = 1MHz

VOC

Video Output Compliance

Voltage

-0.3

2.0

ROUT

Video Output Resistance

Ω

COUT

Video Output Capacitance

IOUT = 0 mA, f = 1 MHz

Parameter

Conditions

Min.

Typ.

Max.

Units

PIPES

Pipeline Delay

PD to Analog Out

PD to DCVBS

PXCK

Periods

tDOZ

Output Delay, CS to low-Z

tDOM

Output Delay, CS to Data Valid

tHOM

Output Hold Time, CS to hi-Z

tDO

Output Delay

PXCK to HSOUT, VSOUT,

PDC, LINE, FLD

D/A Output Current Risetime

10% to 90% of full-scale

D/A Output Current Falltime

90% to 10% of full-scale

tDOV

Analog Output Delay

TMC2193 Datasheet(PDF) 64 Page - Cadeka Microcircuits LLC.

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