TMC2193 datasheet(5/72 Pages) CADEKA

5 / 72 page

PRODUCT SPECIFICATION

TMC2193

REV. 1.0 3/26/03

PXCK

TTL

Pixel Clock Input. PXCK is a clock signal that period is twice

the sample rate of the pixel data. The operating range is 20 to

30 MHz. The clock is internally divided by 2 to generate the

internal pixel clock, PCK. PXCK drives the entire TMC2193

except the asynchronous microprocessor interface.

RESET

TTL

Master Chip Reset. When LOW, All outputs are tri-stated and

the internal state machines and control registers are reset. At

rising edge of RESET, all outputs are active, the preset values

will be loaded into the control registers and the internal states

machines start to operate.

VSIN

TTL

Vertical Sync Input. When operating in slave, Genlock, or

DRS-Lock the TMC2193 will start a new vertical field with each

falling edge of VSIN that is coincident with HSIN.

SYNC & CONTROL OUTPUTS (11 pins)

FLD[2:0]

81–83

TTL

Field Identifier. Field Identifier outputs the current field number.

For all video standards the field identifier will cycle through the

eight counts.

HSOUT

TTL

Horizontal Sync Output. The alignment of HSOUT to the pixel

data port or DCVBS port is controlled by control register

TSOUT.

LINE[4:0]

76–80

TTL

Vertical Blanking Interval Line Identifier. LINE identifies the

current line number for the first 31 lines. If the line count is

greater than 31 then LINE is 11111b. The first line with a vertical

serration is considered to be line 0.

PDC

TTL

Pixel Data Control.

When PDCDIR = LOW: At a rising edge, The next pixel starts a

controlled ramp of the PD data. At a falling edge, the pixel prior

is the last PD used in the ramp. The rising edge is determined

by the PDCCNT control register, the falling edge of PDC is

determined by the horizontal timing registers.

When PDCDIR = HIGH: PDCIN is used to override the internal

PDC. When HIGH, the internal PDC controls the blank and

unblank window. When LOW, the video remains blanked

regardless of the internal PDC. All edges have the same ramp

control as the internal PDC.

VSOUT

TTL

Vertical Sync Output. The alignment of VSOUT to the pixel

data port or DCVBS port is controlled by control register

TSOUT.

DATA INPUTS (39 pins)

CVBS[9:0]

84–93

TTL

Composite Data Input

OL[4:0]

21–25

TTL

Overlay Control

PD[23:0]

27–38, 41–52

TTL

Component Data Input

ANALOG INTERFACE – Video Out (5 pins)

Ref. DAC

0.675Vp-p

Selectable sync only or midpoint reference D/A

DAC1

1.35Vp-p

Composite or Green D/A

DAC2

1.35Vp-p

Luma or Blue D/A

DAC3

1.35Vp-p

Chroma or Red D/A

DAC4

1.35Vp-p

Composite D/A with optional keying

Pin Deﬁnitions (continued)

Pin Name

Pin Number

Value

Description

TMC2193 Datasheet(PDF) 5 Page - Cadeka Microcircuits LLC.

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