MPC2F35L datasheet(10/46 Pages) MEGAWIN

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MPC2F35_USB Data Sheet

MEGAWIN

Overflow signal

WDT

Qw1

Qw2

Qw4

Qw3

RRRR

System Reset

Hardware reset

WDT_CLR.7

WDT_ST.7

Fosc/2^18

System Control Registers

Power saving control

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0200H

PWR_CTL

LVDT

CKC

HALT

√

LVDT: Low-voltage detector disable bit. 1: Disable, 0: Enable (default)

CKC: Oscillator control bit. 1: Disable OSC, 0: Enable OSC (default)

HALT: FCPU off-line control bit. 1: FCPU off-line, 0: FCPU on-line (default)

When the low-voltage detector is enabled, and if it senses the power voltage is lower than 3.3V, then

MPC2F35 will be reset automatically.

Programmer can switch the normal operation mode to the power-saving mode for reducing power

consumption through this register. There are two power saving modes in MPC2F35.

Stop mode: (PWR_CTL.CKC = 1)

System clock stops the built-in oscillator if setting the CKC bit in the PWR_CTL SFR. MPC2F35 can be

awakened from the stop mode by 4 ways: the port 3 interrupt, the hardware reset, the power-on reset

and the USB wake-up.

Halt mode: (PWR_CTL.HALT = 1)

Setting the HALT bit to let the clock source of MPC2F35 to be in the off-line status, but the oscillator

works or not will be depended on the content of the CKC bit in the PWR_CTL SFR.

MPC2F35 can be awakened from the halt mode by 3 ways: the interrupts (USB, Timer 0, Port3, INT0

and INT1) can be assigned by the RLH_EN register, the hardware reset, or the power-on reset.

FCPU selector

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MPC2F35L Datasheet(PDF) 10 Page - Megawin Technology Co., Ltd

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