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MPC2F35L Datasheet(PDF) 27 Page - Megawin Technology Co., Ltd |
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MPC2F35L Datasheet(HTML) 27 Page - Megawin Technology Co., Ltd |
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27 / 46 page  MEGAWIN MPC2F35_USB Data Sheet 27 RXCON: Receive FIFO Control Register (Endpoint-Indexed) Read/Write Address: 24H Default: 0XX0_XXXX System Reset or USB Reset Bit Number Bit Mnemonic Function 7 RXCLR Receive FIFO Clear: Set this bit to flush the entire receive FIFO. All FIFO statuses are reverted to their reset states. Hardware clears this bit when the flush operation is completed. 6 - Reserved: Write zero to this bit. 5 - Reserved: Write zero to this bit. 4 RXFFRC Receive FIFO Read Complete: Set this bit to release the receive FIFO when data set read is complete. Hardware clears this bit after the FIFO release operation has been finished. 3 - Reserved: Write zero to this bit. 2 - Reserved: Write zero to this bit. 1 - Reserved: Write zero to this bit. 0 - Reserved: Write zero to this bit. |
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