AT697F datasheet(65/155 Pages) ATMEL

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AT697F ADVANCE INFORMATION

7703C–AERO–6/09

DSU

Communication

Link

DSU communication link consists of a UART connected to the internal bus as a master.

Figure 39. DSU Communication Link Block Diagram

DSURX

DSUTX

Receiver shift register

Transmitter shift register

AHB master interface

AHB data/response

AMBA AHB

Serial port

Controller

8*bitclk

Baud-rate

generator

AMBA APB

A simple communication protocol is supported to transmit access parameters and data. A link

command consist of a control byte, followed by a 32-bit address, followed by optional write data.

If the TBC LR is set, a response byte will be sent after each AHB transfer. If the TBC LR is not

set, a write access does not return any response, while a read access only returns the read

data.

Data Frame

Data is sent on 8-bit basis.

Figure 40. DSU UART Data Frame

Start

Stop

Commands

Through the communication link, a read or write transfer can be generated to any address on the

internal bus. A response byte is can optionally be sent when the processor goes from execution

mode to debug mode. Block transfers can be performed be setting the length field to n-1, where

n denotes the number of transferred words. For write accesses, the control byte and address is

sent once, followed by the number of data words to be written. The address is automatically

incremented after each data word. For read accesses, the control byte and address is sent once

and the corresponding number of data words is returned.

Figure 41. DSU Commands

DSU Write Command

11 Length -1

Addr[31:24]

Addr[7:0]

Addr[15:8]

Addr[23:16]

Data[31:24]

Data[7:0]

Data[15:8]

Data[23:16]

Send

Receive

10 Length -1

Addr[31:24]

Addr[7:0]

Addr[15:8]

Addr[23:16]

Send

DSU Read command

Resp. byte

(optional)

Receive

Data[31:24]

Data[7:0]

Data[15:8]

Data[23:16]

Resp. byte

(optional)

bit 7:3 = 000000

bit 1:0 = HRESP

Response byte encoding

bit 2 = DMODE

Clock Generation

The UART contains a 14-bit down-counting scaler to generate the desired baud-rate. The scaler

is clocked by the system clock and generates a UART tick each time it underflows. The scaler is

reloaded with the value of the UART scaler reload register after each underflow. The resulting

UART tick frequency should be 8 times the desired baud-rate.

AT697F Datasheet(PDF) 65 Page - ATMEL Corporation

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