AT697F datasheet(34/155 Pages) ATMEL

34 / 155 page

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

The Auto-Refresh command enables a periodical refresh for both SDRAM banks. The period

between two Auto-Refresh command is programmed in MCFG3 SRCRV.

Depending on SDRAM type, required period is typically 7.8 or 15.6

μs. This corresponds to 780

or 1560 clock cycle at 100MHz.

Refresh period is calculated as

Refresh Period

Reload value

sdclk frequency

--------------------------------------------

SDRAM Initialisation

After reset, the SDRAM controller automatically performs the SDRAM initialisation sequence. It

consists in PRECHARGE, two AUTO-REFRESH cycles and LOAD-MODE-REG on both banks

simultaneously.

The controller programs the SDRAM to use page burst on read and single location access on

write. A CAS latency of 3 is programmed by default. This value can be updated later by

software.

SDRAM Read Access

A read transaction consists in three main operation. First, an ACTIVATE command to the

desired bank and row is performed. Then, after the programmed CAS delay, a READ command

is sent. The read transaction is terminated with a PRE-CHARGE command. No bank is left open

between two accesses.

A burst read is performed if a burst access is requested on the internal bus.

SDRAM Write Access

A write transactions consists in three main operations. First, an ACTIVATE command to the

desired bank and row is performed. Then, a WRITE command is sent. The write transaction is

terminated with the PRE-CHARGE command.

A burst write on internal bus generates a burst of write commands without idle cycles in-

between.

Access Error

An access error can be indicated to the processor asserting the BEXC* signal. If enabled by set-

ting logical one to MCFG1 BEXC , the BEXC* signal is sampled with the data.

If the BEXC* signal is driven low by the external device during the access, an error response is

generated on the internal bus.

•

Trap 0x01 is taken if an instruction fetch is in progress

•

Trap 0x09 is taken if a data space access is in progress

•

Trap 0x2B is taken if a data store is in progress

AT697F Datasheet(PDF) 34 Page - ATMEL Corporation

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