AT697F datasheet(40/155 Pages) ATMEL

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7703C–AERO–6/09

AT697F ADVANCE INFORMATION

Error Management

- EDAC

Overview

The AT697F processor implements an on-chip error detector and corrector (EDAC). The on-chip

memory EDAC can correct one error in a 32-bit word and detect two errors in a 32-bit word. The

processor EDAC implemention enables data correction on-the-fly so that no timing penalty

occurs during correction.

EDAC capability

mapping

Data error management with the EDAC can be used on both PROM and RAM memory areas.

The following table presents the EDAC protection capabilities provided by the processor.

Table 16.

Address Range

Area

EDAC Protected

0x00000000 - 0x1FFFFFFF

PROM

8 bits

yes

32 bits

yes

0x20000000 - 0x3FFFFFFF

I/O

All

0x40000000 - 0x7FFFFFFF

RAM

8 bits

yes

32 bits

yes

EDAC capability on Memories

PROM protection

Setting logical one the PROM EDAC enable bit MCFG3 PE, the data protection is enabled. For

each read and write transaction to the PROM area the EDAC act as an error detector and an

error corrector. When set logical zero, the EDAC is transparent for the PROM access.

At power-on or at reset, the value of the MCFG3 PE is directly copied from the PIO2 pin. In that

way, it is possible to start the application with the EDAC enabled by driving high PIO2 during the

power-on sequence (or reset sequence).

RAM protection

Setting logical one the RAM EDAC enable bit MCFG3 RE, the data protection is enabled. For

each read and write transaction to the RAM area the EDAC act as an error detector and an error

corrector. When set logical zero, the EDAC is transparent for the RAM access.

Operation

The processor uses an EDAC based on a seven bit Hamming code that detects any double error

on a 32-bit bus and corrects any single error on a 32-bit bus. Note when the EDAC is enabled

the read-modify-write bit MCFG2 RMW must be set.

Hamming code

For each 32-bit data, a seven bit a 7-bit checksum is generated. The equations below show how

the Hamming checkbits (CBx) are generated:

CB0 = D0 ^ D4 ^ D6 ^ D7 ^ D8 ^ D9 ^ D11 ^ D14 ^ D17 ^ D18 ^ D19 ^ D21 ^ D26 ^ D28 ^ D29 ^ D31

CB1 = D0 ^ D1 ^ D2 ^ D4 ^ D6 ^ D8 ^ D10 ^ D12 ^ D16 ^ D17 ^ D18 ^ D20 ^ D22 ^ D24 ^ D26 ^ D28

CB2 = D0 ^ D3 ^ D4 ^ D7 ^ D9 ^ D10 ^ D13 ^ D15 ^ D16 ^ D19 ^ D20 ^ D23 ^ D25 ^ D26 ^ D29 ^ D31

CB3 = D0 ^ D1 ^ D5 ^ D6 ^ D7 ^ D11 ^ D12 ^ D13 ^ D16 ^ D17 ^ D21 ^ D22 ^ D23 ^ D27 ^ D28 ^ D29

CB4 = D2 ^ D3 ^ D4 ^ D5 ^ D6 ^ D7 ^ D14 ^ D15 ^ D18 ^ D19 ^ D20 ^ D21 ^ D22 ^ D23 ^ D30 ^ D31

CB5 = D8 ^ D9 ^ D10 ^ D11 ^ D12 ^ D13 ^ D14 ^ D15 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31

CB6 = D0 ^ D1 ^ D2 ^ D3 ^ D4 ^ D5 ^ D6 ^ D7 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31

Write operation

When the processor performs a write operation to a memory protected by the EDAC, it also out-

puts the seven bit checksum on the CB[6:0] pins.

Read operation

During a read operation from a protected memory, the seven bit checksum is sampled from the

CB[6:0] inputs. Then, the EDAC verify the checksum to check the presence of an error.

According to the checksum equations, the EDAC calculates its own checksum. Then a syn-

drome generator uses the calculated and the read checksum to qualify if there is no error, one

error or two errors in the read word.

Correctable error

If a single error is detected, this leads to a correctable error. The correction is done on-the-fly

during the current access and no timing penalty is induced but the corrected data is not automat-

ically written back to the memory.

AT697F Datasheet(PDF) 40 Page - ATMEL Corporation

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