AT697F datasheet(44/155 Pages) ATMEL

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7703C–AERO–6/09

AT697F ADVANCE INFORMATION

Overview

The AT697F instruction cache is a multi-set cache of 32 kbyte divided in 4 memory sets. Multi-

set-cache use improves speed performance of the core. The instruction cache is divided into

cache lines with 32 bytes of data. Each line has a cache tag associated with it consisting of a tag

field and one valid bit per 4-byte sub-block.

Cache Control

The instruction cache operations are controled with the cache control register (CCR).

Operation

On an instruction cache miss to a cachable location, the instruction is fetched and the corre-

sponding tag and data line updated. The instruction cache always works in one of three modes:

•

disabled,

•

enabled

•

or frozen.

The instruction cache current state is reported in the instruction cache state CCR ICS.

Disabled mode

If disabled, no cache operation is performed and load and store requests are passed directly to

the memory controller.

Enabled mode

If enabled, the cache operates as described above. In the frozen state, the cache is accessed

and kept in synchronisation with the main memory as if it was enabled, but no new lines are allo-

cated on read misses.

Freeze mode

If CCR IF is set logical one, the instruction cache is frozen when an asynchronous interrupt is

taken. This can be beneficial in real-time system to allow a more accurate calculation of worst-

case execution time for a code segment. The execution of the interrupt handler will not evict any

cache lines and when control is returned to the interrupted task, the cache state is identical to

what it was before the interrupt.

If a cache has been frozen by an interrupt, it can only be enabled again by enabling the cache in

the CCR. This is typically done at the end of the interrupt handler before control is returned to

the interrupted task.

Burst fetch

An instruction burst fetch mode can be enabled setting logical one in CCR IB. If the burst fetch

is enabled, the cache line is filled from main memory starting at the missed address and until the

end of the line. At the same time, the instructions are forwarded to the IU. If the IU cannot accept

the streamed instructions due to internal dependencies or multi-cycle instruction, the IU is halted

until the line fill is completed.

If the IU executes a control transfer instruction during the line fill, the line fill will be terminated on

the next fetch. If instruction burst fetch is enabled, instruction streaming is enabled even when

the cache is disabled. In this case, the fetched instructions are only forwarded to the IU and the

cache is not updated.

Cache Flush

Instruction cache can be flushed by executing the FLUSH instruction, setting logical one in

CCR FI, or writing any location with ASI=0x5. The flush operation takes one cycle per line dur-

ing which the IU will is not halted, but during which the cache is disabled. When the flush

operation is completed, the cache will resume the state indicated in the cache control register.

Error reporting

If a memory access error occurs during a line fill with the IU halted, the corresponding valid bit in

the cache tag is not set. If the IU later fetches an instruction from the failed address, a cache

miss will occur, triggering a new access to the failed address.

If the error remains, an instruction access error trap (tt=0x1) is generated.

Instruction Cache

Parity

Error detection of cache tags and data is implemented using two parity bits per tag and per 4-

byte data sub-block. The tag parity is generated from the tag value and the valid bits. The data

parity is derived from the sub-block data. The parity bits are written simultaneously with the

associated tag or sub-block and checked on each access. The two parity bits correspond to the

parity of odd and even data (tag) bits.

AT697F Datasheet(PDF) 44 Page - ATMEL Corporation

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