AT697F datasheet(85/155 Pages) ATMEL

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AT697F ADVANCE INFORMATION

7703C–AERO–6/09

Memory Interface

Registers

Table 45. Memory Configuration Register 1 - MCFG1

Address = 0x80000000

r/w r/w r/w

r/w

r/w r/w r/w

r/w

r/w r/w

r/w

xxx

xxx xxxx

1111

Bit Number

Mnemonic

Description

pbrdy

PROM area bus ready enable

if set, a PROM access will be extended until BRDY* is asserted (driven low).

abrdy

Asynchronous bus ready

If set, the BRDY* input can be asserted without relation to the sysstem clock, provided it is at least 1.5 clock

cycles long. Termination of the access after assertion of BRDY* will be delayed by at least one clock cycle.

28:27

iowdh[1:0]

I/O bus width.

Defines the data with of the I/O area (“00”=8, “10”=32).

iobrdy

IO area bus ready enable

if set to one, an IO access will be extended until BRDY* is asserted (Driven low)

bexc

Bus error enable for RAM, PROM and IO transactions.

If set to one, the (low) assertion of the BEXC* will generate an error response on the internal bus and causes a

trap (0x01, 0x09, 0x2B) depending on the type of access.

23:20

iows[3:0]

I/O waitstates.

Defines the number of waitstates during I/O accesses:

“0000” = 0 waitstate,

“0001” = 1 waitstates,

...,

“1111” = 15 waitstates.

iop

I/O protection.

‘0’ : Read and write accesses to I/O area are disabled

‘1’ : Read and write accesses to I/O area are enabled.

prwen

Prom write enable.

If set, enables write cycles to the prom area.

9:8

prwdh[1:0]

Prom width.

Defines the data with of the prom area:

“00” = 8 bits,

“10” = 32 bits.

7..4

prwws[3:0]

Prom write waitstates.

Defines the number of waitstates during prom write cycles:

“0000” = 0 waitstate,

“0001” = 2 waitstates,

...,

“1111” = 30 waitstates.

3..0

prrws[3:0]

Prom read waitstates.

Defines the number of waitstates during prom read cycles

“0000” = 0 waitstate,

“0001” = 2 waitstates,

...,

“1111” = 30waitstates.

AT697F Datasheet(PDF) 85 Page - ATMEL Corporation

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