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DM9801A Datasheet(PDF) 1 Page - Davicom Semiconductor, Inc. |
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DM9801A Datasheet(HTML) 1 Page - Davicom Semiconductor, Inc. |
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1 / 60 page  DM9801A 1M Home Phoneline Network Physical Layer Single Chip Transceiver Final 1 Version: DM9801A-DS-F01 May 30, 2001 General Description The DM9801A is a physical-layer, single-chip, low-power transceiver for 1M Home Phoneline Network applications. On the media side, it provides an interface to a Home Phoneline wiring system. The reconciliation layer interfaces to the DM9801A either through an IEEE802.3u subset Media Independent Interface (MII) or a pseudo-standard General Purpose Serial Interface (GPSI). A management interface is provided by MDIO/MDC when operating in MII mode, or a Serial Peripheral Interface bus when operating in GPSI mode. The DM9801A uses a low-power and high-performance CMOS process. It contains the entire physical layer functions of 1M as defined by Home Phoneline Network Alliance, Rev. 1.1, including the Physical Coding Sublayer, (RLL25) Encoder/Decoder (ENC/DEC), 4-wire HN Driver circuit and receiver analog front end (AFE). Patent-Pending Circuitry Includes: Enhanced 4-wire Home Network transceiver circuit. Compatible with HomePNA 1M PHY specification version 1.1 and HomePNA certification document version 1.0 Block Diagram HN Secondary Driver Muxed GPSI or Mii Interface RLL25 Encoder RLL25 Decoder Master PHY Controller Receiever and Digital PLL Transmit Timing Generator HN Primary Driver Receiver AFE GPSI - MII Transmit GPSI - MII Receive HNA+/- HNB+/- Interface Select |
Similar Part No. - DM9801A |
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Similar Description - DM9801A |
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