DM9801A datasheet(21/60 Pages) DAVICOM

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DM9801A

1M Home Phoneline Network Physical Layer Single Chip Transceiver

Final

Version: DM9801A-DS-F01

May 30, 2001

Serial Peripheral Interface (SPI) Bus

When INTFSEL is asserted, the DM9801A is

configured to operate in SPI mode. While

configured to operate in SPI mode, the DM9801A

can act as a SPI Slave or SPI Master. Asserting

SMODE places the DM9801A in SPI Slave mode.

Clearing SMODE places the DM9801A in SPI

Master Mode.

The SPI (Serial Peripheral Interface) Bus uses a

four-wired serial interface to obtain and control the

status of the physical layer through the SPI Bus

interface. The serial control interface consists of SI

(serial data input), SO (serial data output), SCLK

(serial clock), and SCS# (serial interface chip

select) signals. When operating in Master mode the

DM9801A drives the SCLK and SCS# signals,

when operating in Slave mode these signals are

inputs.

SPI-Slave Mode (Valid only in GPSI Mode)

When SMODE is asserted the DM9801A is

configured for SPI Slave operation. Commands are

issued to the DM9801A by asserting the SCS#

signal, shifting in an 8-bit opcode followed by a

operation is a write, the address is followed by an 8-

bit data byte. If the operation is a read, the SO pin

will shift out an 8-bit data byte representing the

contents of the register referenced by the address

field. Only one command can be sent in one SCS#

cycle. The DM9801A does not support multiple byte

reads or writes.

SPI-Master Mode (Valid only in GPSI Mode)

When SMODE is cleared the DM9801A is

configured for SPI Master operation. When the

DM9801A is configured for SPI-Master operation, it

will load all programmable registers from an

external SPI type EEPROM. The memory locations

loaded may be offset via the boot page pins,

BP[1:0], allowing a single 256 byte serial EEPROM

to hold four distinct sets of default register values.

After RESET# has cleared the DM9801A will assert

SCS#, shift out a Read opcode (0x03), followed by

the initial address to be read (as modified by the

Boot Page pins). The DM9801A will then shift in the

memory contents, auto incrementing the register

address being programmed every 8-bits. Once all

64-bytes have been read, the DM9801A releases

SCS#. The SCLK continues to run. Opcodes are

shown in Table 1.

Instruction Format

Instruction Name

0000 0110

Set WE

0000 0100

Clear WE

0000 0011

Read

0000 0010

Write

OPCODES

Table 1

DM9801A Datasheet(PDF) 21 Page - Davicom Semiconductor, Inc.

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