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SFSL5.5MDB Datasheet(PDF) 3 Page - Yamar Electronics Ltd. |
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SFSL5.5MDB Datasheet(HTML) 3 Page - Yamar Electronics Ltd. |
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3 / 12 page ![]() Proprietary and Confidential Information of YAMAR Electronics Ltd. @ 2007 Yamar Electronics Ltd. 3 DS-SIG40 R1.8 3 SIG40 SIGNALS The SIG40 Signals are divided into three main functions: • Host input / output • Line interface • Sleep mechanism Figure 3.1 describes the interconnections between SIG40 its host, the ceramic filters and the DC line. Figure 3.1 - Interfacing the SIG40 Device signals are defined in table 3.1. Table 3.1 - Device signals Host I/O signals Line Interface signals HDO Data Output 1 MF0nF1 F0/F1 selected Output 10 INH Inhibit operation Output 2 OscOut Crystal Output 12 HDI Data Input 3 OscIn Crystal Input 13 nSleep Sleep Input 4 RxN Rx Analog - Input 15 HDC Data/Command Input 5 RxP Rx Analog + Input 16 nReset Reset Input 6 DTxO Transmit data Output 18 Wake Wakeup Input 7 TxOn Transmit On Output 19 InterfHop Allow Interference hopping Input 8 RxOn Receive On Output 20 Power signals Vcc Power 14 Gnd Power 17 GndPLL Ground for PLL 11 VccPLL Vcc for PLL 9 3.1 Host interface Three lines are dedicated for Host data input / output and for command. 3.1.1 HDI Data input signal to the SIG40. Transfer data from host to SIG40. When not in use should be pulled Up. 3.1.2 HDO Data output signal from SIG40. Transfers received data to host. 3.1.3 HDC Data/Command mode. When Low, enables read and write to internal registers. When not in use should be pulled Up. Ceramic Filter Ceramic Filter II SIG40 DC-Line ~Data/Control HDI UART HOST LIN Controller Crystal nSleep INH HDC Wake HDO MF0nF1 InterfHop Line Interface TxOn DTxO RxOn DRxP |
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