PIC12CE519-04SLASHESM datasheet(33/113 Pages) MICROCHIP

33 / 113 page

DS40139E-page 33

PIC12C5XX

7.3

WRITE OPERATIONS

7.3.1

BYTE WRITE

Following the start signal from the master, the device

code (4 bits), the don’t care bits (3 bits), and the R/W

bit (which is a logic low) are placed onto the bus by the

master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will follow

after it has generated an acknowledge bit during the

ninth clock cycle. Therefore, the next byte transmitted

by the master is the word address and will be written

into the address pointer. Only the lower four address

bits are used by the device, and the upper four bits are

don’t cares. The address byte is acknowledgeable and

the master device will then transmit the data word to be

written into the addressed memory location. The mem-

ory acknowledges again and the master generates a

stop condition. This initiates the internal write cycle,

and during this time will not generate acknowledge sig-

nals (Figure 7-7). After a byte write command, the inter-

nal address counter will not be incremented and will

point to the same address location that was just written.

If a stop bit is transmitted to the device at any point in

the write command sequence before the entire

sequence is complete, then the command will abort

and no data will be written. If more than 8 data bits are

transmitted before the stop bit is sent, then the device

will clear the previously loaded byte and begin loading

the data buffer again. If more than one data byte is

transmitted to the device and a stop bit is sent before a

full eight data bits have been transmitted, then the write

command will abort and no data will be written. The

EEPROM memory employs a VCC threshold detector

circuit which disables the internal erase/write logic if the

VCC is below minimum VDD.

Byte write operations must be preceded and immedi-

ately followed by a bus not busy bus cycle where both

SDA and SCL are held high.

7.4

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed write cycle. ACK polling can

be initiated immediately. This involves the master send-

ing a start condition followed by the control byte for a

write command (R/W = 0). If the device is still busy with

the write cycle, then no ACK will be returned. If no ACK

is returned, then the start bit and control byte must be

re-sent. If the cycle is complete, then the device will

return the ACK and the master can then proceed with

the next read or write command. See Figure 7-6 for

flow diagram.

FIGURE 7-6:

ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

FIGURE 7-7:

BYTE WRITE

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

WORD

ADDRESS

DATA

X = Don’t Care Bit

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