ADT7476ARQZ-R7 datasheet(52/67 Pages) ONSEMI

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ADT7476

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Table 22. Register 0x40 — Configuration Register 1 (Power−On Default = 0x04)

Bit No.

Mnemonic

R/W

Description

[0]

STRT

(Notes 1, 2)

R/W

Logic 1 enables monitoring and PWM control outputs based on the limit settings

programmed.

Logic 0 disables monitoring and PWM control is based on the default powerup limit settings.

Note that the limit values programmed are preserved even if a Logic 0 is written to this bit

and the default settings are enabled. This bit does not become locked once Bit 1 (LOCK bit)

has been set.

[1]

LOCK

Write once

Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers

become read−only and cannot be modified until the ADT7476 is powered down and powered

up again. This prevents rogue programs such as viruses from modifying critical system limit

settings. (Lockable.)

[2]

RDY

Read−only

This bit is set to 1 by the ADT7476 to indicate that the device is fully powered−up and ready

to begin system monitoring.

[3]

FSPD

R/W

When set to 1, this bit runs all fans at max speed as programmed in the max PWM current

duty cycle registers (0x30 to 0x32). Power−on default = 0. This bit is not locked at any time.

[4]

Vx1

R/W

BIOS should set this bit to a 1 when the ADT7476 is configured to measure current from an

ADOPT

® VRM controller and to measure the CPU’s core voltage. This bit allows monitoring

software to display CPU watts usage. (Lockable.)

[5]

FSPDIS

R/W

Logic 1 disables fan spin−up for two TACH pulses. Instead, the PWM outputs go high for the

entire fan spin−up timeout selected.

[6]

TODIS

R/W

When this bit is set to 1, the SMBus timeout feature is enabled. In this state, if at any point

during an SMBus transaction involving the ADT7476 activity ceases for more than 35 ms, the

ADT7476 assumes the bus is locked and releases the bus. This allows the ADT7476 to be

used with SMBus controllers that cannot handle SMBus timeouts. (Lockable.)

[7]

Reserved

N/A

Reserved. Do not write to this bit.

1. Bit 0 (STRT) of Configuration Register 1 (0x40) remains writable after lock bit is set.

2. When monitoring (STRT) is disabled, PWM outputs always go to 100% for thermal protection.

Table 23. Register 0x41 — Interrupt Status Register 1 (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W

Description

[0]

2.5 V/

THERM

Read−only

2.5 V = 1 indicates that the 2.5 V high or low limit has been exceeded. This bit is cleared on a

read of the status register only if the error condition has subsided. If Pin 22 is configured as

THERM, this bit is asserted when the timer limit has been exceeded.

[1]

VCCP

Read−only

VCCP = 1 indicates that the VCCP high or low limit has been exceeded. This bit is cleared on

a read of the status register only if the error condition has subsided.

[2]

VCC

Read−only

VCC = 1 indicates that the VCC high or low limit has been exceeded. This bit is cleared on a

read of the status register only if the error condition has subsided.

[3]

5.0 V

Read−only

A 1 indicates that the 5.0 V high or low limit has been exceeded. This bit is cleared on a read

of the status register only if the error condition has subsided.

[4]

R1T

Read−only

R1T = 1 indicates that the Remote 1 low or high temperature has been exceeded. This bit is

cleared on a read of the status register only if the error condition has subsided.

[5]

Read−only

LT = 1 indicates that the local low or high temperature has been exceeded. This bit is cleared

on a read of the status register only if the error condition has subsided.

[6]

R2T

Read−only

R2T = 1 indicates that the Remote 2 low or high temperature has been exceeded. This bit is

cleared on a read of the status register only if the error condition has subsided.

[7]

OOL

Read−only

OOL = 1 indicates that an out−of−limit event has been latched in Interrupt Status Register 2.

This bit is a logical OR of all status bits in Interrupt Status Register 2. Software can test this

bit in isolation to determine whether any of the voltage, temperature, or fan speed readings

represented by Interrupt Status Register 2 are out−of−limit, which eliminates the need to read

Interrupt Status Register 2 during every interrupt or polling cycle.

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