ADT7476ARQZ-R7 datasheet(55/67 Pages) ONSEMI

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ADT7476

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Table 30. PWM Configuration Registers

R/W (Note 1)

Description

Power−On Default

0x5C

R/W

PWM1 configuration

0x62

0x5D

R/W

PWM2 configuration

0x62

0x5E

R/W

PWM3 configuration

0x62

Bit No.

Name

R/W

Description

[2:0]

SPIN

R/W

These bits control the startup timeout for PWMx. The PWM output stays high until two valid

TACH rising edges are seen from the fan. If there is not a valid TACH signal during the fan

TACH measurement directly after the fan startup timeout period, the TACH measurement

reads 0xFFFF and Interrupt Status Register 2 reflects the fan fault. If the TACH minimum

high and low bytes contain 0xFFFF or 0x0000, the Interrupt Status Register 2 bit is not set,

even if the fan has not started.

000 = No startup timeout

001 = 100 ms

010 = 250 ms (default)

011 = 400 ms

100 = 667 ms

101 = 1 sec

110 = 2 sec

111 = 4 sec

[3]

RES

N/A

Reserved. Do not write to this bit.

[4]

INV

R/W

This bit inverts the PWM output. The default is 0, which corresponds to a logic high output for

100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100% duty cycle

corresponds to a logic low output.

[7:5]

BHVR

R/W

These bits assign each fan to a particular temperature sensor for localized cooling.

000 = Remote 1 temperature controls PWMx (automatic fan control mode).

001 = Local temperature controls PWMx (automatic fan control mode).

010 = Remote 2 temperature controls PWMx (automatic fan control mode).

011 = PWMx runs full speed (default).

100 = PWMx disabled.

101 = Fastest speed calculated by local and Remote 2 temperature controls PWMx.

110 = Fastest speed calculated by all three temperature channel controls PWMx.

111 = Manual mode. PWM current duty cycle registers (0x30 to 0x32) become writable.

1. These registers become read−only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.

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