ADT7476ARQZ-R7 datasheet(24/67 Pages) ONSEMI

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ADT7476

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Figure 32. Understanding the THERM Timer

THERM

TIMER

(REG. 0x79)

THERM ASSERTED

v 22.76ms

765

321 0

000

000 1

THERM

TIMER

(REG. 0x79)

THERM ASSERTED

w 45.52ms

765

321 0

000

001 0

THERM

TIMER

(REG. 0x79)

THERM ASSERTED w 113.8ms

(91.04ms + 22.76ms)

765

321 0

000

010 1

THERM

ACCUMULATE THERM LOW

ASSERTION TIMES

THERM

ACCUMULATE THERM LOW

ASSERTION TIMES

When using the THERM timer, be aware of the following:

After a THERM timer read (0x79)

1. The contents of the timer are cleared on read.

2. The F4P bit (Bit 5) of Interrupt Status Register 2

needs to be cleared (assuming that the THERM

timer limit has been exceeded).

If the THERM timer is read during a THERM assertion, the

following occurs:

1. The contents of the timer are cleared.

2. Bit 0 of the THERM timer is set to 1, because a

THERM assertion is occurring.

3. The THERM timer increments from zero.

4. If the THERM timer limit register (0x7A) = 0x00,

the F4P bit is set.

Generating SMBALERT Interrupts from THERM Timer

Events

The ADT7476 can generate SMBALERTs when a

programmable THERM timer limit has been exceeded. This

allows the system designer to ignore brief, infrequent

THERM assertions, while capturing longer THERM timer

events. Register 0x7A is the THERM timer limit register.

This 8−bit register allows a limit from 0 sec (first THERM

assertion) to 5.825 sec to be set before an SMBALERT is

generated. The THERM timer value is compared with the

contents of the THERM timer limit register. If the THERM

timer value exceeds the THERM timer limit value, then the

F4P bit (Bit 5) of Interrupt Status Register 2 is set and an

SMBALERT is generated.

Note: Depending on which pins are configured as a

THERM timer, setting the F4P bit (Bit 5) of Mask Register 2

(0x75) or Bit 0 of Mask Register 1 (0x74) masks out

SMBALERT; although the F4P bit of Interrupt Status

Figure 33 is a functional block diagram of the THERM

timer, limit, and associated circuitry. Writing a value of 0x00

to the THERM timer limit register (0x7A) causes an

SMBALERT to be generated on the first THERM assertion.

A THERM timer limit value of 0x01 generates an

SMBALERT once cumulative THERM assertions exceed

45.52 ms.

Figure 33. Functional Block Diagram of THERM Monitoring Circuitry

22.76ms

45.52ms

91.04ms

182.08ms

364.16ms

728.32ms

1.457s

2.914s

OUT

RESET

LATCH

CLEARED

ON READ

F4P BIT (BIT 5)

MASK REGISTER 2

(REG. 0x75)

1 = MASK

F4P BIT (BIT 5)

STATUS REGISTER 2

COMPARATOR

22.76ms

45.52ms

91.04ms

182.08ms

364.16ms

728.32ms

1.457s

2.914s

7 6 543 2 1 0

THERM LIMIT

(REG. 0x7A)

THERM TIMER

(REG. 0x79)

THERM TIMER CLEARED ON READ

SMBALERT

THERM

ADT7476ARQZ-R7 Datasheet(PDF) 24 Page - ON Semiconductor

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