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ADT7476ARQZ-R7 Datasheet(PDF) 58 Page - ON Semiconductor |
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ADT7476ARQZ-R7 Datasheet(HTML) 58 Page - ON Semiconductor |
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58 / 67 page ![]() ADT7476 http://onsemi.com 58 Table 33. Register 0x63 — Enhanced Acoustics Register 2 (Power−On Default = 0x00) Bit No. Mnemonic R/W (Note 1) Description [2:0] ACOU3 R/W Assuming that PWMx is associated with the local temperature channel, these bits define the maximum rate of change of the PWMx output for local temperature related changes. Instead of the fan speed jumping instantaneously to its newly determined speed, it ramps gracefully at the rate determined by these bits. This feature ultimately enhances the acoustics of the fan. When Bit 7 of Configuration Register 6 (0x10) is 0 Time Slot Increase Time for 0% to 100% 000 = 1 001 = 2 010 = 3 011 = 4 100 = 8 101 = 12 110 = 24 111 = 48 37.5 sec 18.8 sec 12.5 sec 7.5 sec 4.7 sec 3.1 sec 1.6 sec 0.8 sec When Bit 7 of Configuration Register 6 (0x10) is 1 Time Slot Increase Time for 0% to 100% 000 = 1 001 = 2 010 = 3 011 = 4 100 = 8 101 = 12 110 = 24 111 = 48 52.2 sec 26.1 sec 17.4 sec 10.4 sec 6.5 sec 4.4 sec 2.2 sec 1.1 sec [3] EN3 R/W When this bit is 1, smoothing is enabled on the local temperature channel. [6:4] ACOU2 R/W Assuming that PWMx is associated with the Remote 2 temperature channel, these bits define the maximum rate of change of the PWMx output for Remote 2 Temperature related changes. Instead of the fan speed jumping instantaneously to its newly determined speed, it ramps gracefully at the rate determined by these bits. This feature ultimately enhances the acoustics of the fan. [2:0] ACOU3 R/W When Bit 7 of Configuration Register 6 (0x10) is 0 Time Slot Increase Time for 0% to 100% 000 = 1 001 = 2 010 = 3 011 = 4 100 = 8 101 = 12 110 = 24 111 = 48 37.5 sec 18.8 sec 12.5 sec 7.5 sec 4.7 sec 3.1 sec 1.6 sec 0.8 sec When Bit 7 of Configuration Register 6 (0x10) is 1 Time Slot Increase Time for 0% to 100% 000 = 1 001 = 2 010 = 3 011 = 4 100 = 8 101 = 12 110 = 24 111 = 48 52.2 sec 26.1 sec 17.4 sec 10.4 sec 6.5 sec 4.4 sec 2.2 sec 1.1 sec [7] EN2 R/W When this bit is 1, smoothing is enabled on the Remote 2 temperature channel. 1. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. |
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