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MC68HC705P9CS Datasheet(PDF) 157 Page - Freescale Semiconductor, Inc |
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MC68HC705P9CS Datasheet(HTML) 157 Page - Freescale Semiconductor, Inc |
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157 / 160 page ![]() Index MOTOROLA Index 157 PC7/VRH pin . . . . . . . . . . . . . . . . . . . .88, 131 PD5 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 PD7 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 PD7/TCAP pin . . . . . . .39, 90, 103, 110–111 pin assignments . . . . . . . . . . . . . . . . . . . . .26 pin functions . . . . . . . . . . . . . . . . . . . . . . . .26 port A . . . . . . . . . . . . . . . . . . . . . . . . . .29, 83 data direction register A (DDRA) . . . . .83 port A data register (PORTA) . . . . . . . .83 port B . . . . . . . . . . . . . . . . . . . . . . . . . .29, 85 data direction register B (DDRB) . . . . .86 port B data register (PORTB) . . . . . . . .85 port C . . . . . . . . . . . . . . . . . . . . . . . . . .29, 87 data direction register C (DDRC) . . . . .89 port C data register (PORTC) . . . . . . . .88 port D . . . . . . . . . . . . . . . . . . . . . . . . . .29, 90 data direction register D (DDRD) . . . . .92 port D data register (PORTD) . . . . . . . .91 ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 parallel I/O port register summary . . . . .82 port A . . . . . . . . . . . . . . . . . . . . . . . . . .83 port B . . . . . . . . . . . . . . . . . . . . . . . . . .85 port C . . . . . . . . . . . . . . . . . . . . . . . . . .87 port D . . . . . . . . . . . . . . . . . . . . . . . . . .90 power dissipation . . . . . . . . . . . . . . .136, 140 power supply (VDD) . . . . . . . . . . . . . . .26, 41 power supply (VPP) . . . . . . . . . . . . . . . . . .41 power-on reset . . . . . . . . . . . . . . . . . . . . . .66 program counter (PC) . . . . . . . .52, 55, 66, 72 programmable options COP watchdog enable/disable . . . .22, 96 external interrupt pin triggering . . . .22, 42 SIOP data format . . . . . . . . . . . . .22, 120 Q quartz window . . . . . . . . . . . . . . . . . . . . . .37 R RAM locations . . . . . . . . . . . . . . . . . . . . . . . .36 stack . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Reading . . . . . . . . . . . . . . . . . . . . . . . . . . 112 registers ADC I/O register summary . . . . . . . . .131 CPU registers . . . . . . . . . . . . . . . . . . . .45 parallel I/O port register summary . . . . 82 parallel I/O register summary . . . . . . . . 33 SIOP I/O register summary . . . . . . . . 119 timer I/O register summary . . . . . . . . .102 RESET pin . . . . . . . . . . . . . . . . 28, 39, 66–68 reset sources COP watchdog . . . . . . . . . . . . . . . . . . . 66 power-on . . . . . . . . . . . . . . . . . . . . . . . .66 RESET pin . . . . . . . . . . . . . . . . . . . . . . 66 reset vector . . . . . . . . . . . . . . . . . . . . . . . .66 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 COP watchdog reset . . . . . . . . . . . 68, 96 COP watchdog reset operation . . . . . . 96 external reset . . . . . . . . . . . . . . . . . . . . 67 external reset timing . . . . . . . . . . . . . . .67 low-voltage protection reset . . . . . . . . . 68 power-on reset (POR) . . . . . . . . . . . . . 66 power-on reset (POR) timing . . . . . . . . 67 reset sources . . . . . . . . . . . . . . . . . . . . 66 reset/interrupt vector addresses . . . . . .73 S SIOP (serial input/output port) block diagram . . . . . . . . . . . . . . . . . . .119 description . . . . . . . . . . . . . . . . . . . . . 118 features . . . . . . . . . . . . . . . . . . . . . . . . 118 I/O register summary . . . . . . . . . . . . . 119 I/O registers . . . . . . . . . . . . . . . . . . . . 125 low-power modes . . . . . . . . . . . . . . . . 128 operation . . . . . . . . . . . . . . . . . . . . . . .120 timing . . . . . . . . . . . . . . . . . . . . . 123–124 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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