MC68HC705P9CS datasheet(155/160 Pages) FREESCALE

155 / 160 page

Index

MOTOROLA

Index

155

PC[7:0] bits . . . . . . . . . . . . . . . . . . . . . .88

PD5 bit . . . . . . . . . . . . . . . . . . . . . . . . .91

PD7 bit . . . . . . . . . . . . . . . . . . . . . . . . .91

SIOP bit . . . . . . . . . . . . . . . . . . . . . . . . .42

SPE bit . . . . . . . . . . . .121–122, 125, 127

SPIF bit . . . . . . . . . . . . . . . . . . . . . . . .126

TOF bit . . . . . . . . . . . . .71, 108, 111–113

TOIE bit . . . . . . . . . . . . . . . . .71, 108–109

I/O pins

IRQ/VPP pin . . . . . .22, 29, 38–39, 42, 69

OSC1 pin . . . . . . . . . . . . . . . . . . . . . . .27

OSC2 pin . . . . . . . . . . . . . . . . . . . . . . .27

PB5/SDO pin . . . . . . . . .86, 120–122, 125

PB6/SDI pin . . . . . . . . .86, 120–122, 125

PB7/SCK pin . . . . . . . . .85, 120–122, 125

PC3/AN0 pin . . . . . . . . . . . . . . . . . . . .135

PC3/AN3 pin . . . . . . . . . . . . . . . . .88, 131

PC4/AN2 pin . . . . . . . . . . . . .88, 131, 135

PC5/AN1 pin . . . . . . . . . . . . .88, 131, 135

PC6/AN0 pin . . . . . . . . . . . . .88, 131, 135

PC7/VRH pin . . . . . . . . . . . . . . . . .88, 131

PD7/TCAP pin . . . . .39, 90, 103, 110–111

RESET pin . . . . . . . . . . . . .28, 39, 66–68

TCMP pin . . . . . . .29, 103–104, 110, 115

VSS pin . . . . . . . . . . . . . . . . . . . . . . . . .26

I/O port pin termination . . . . . . . . . . . . . . . .81

I/O registers

ADC data register (ADDR) .132, 134–136

ADC status and control

alternate timer registers (ATRH/L) . . .113

COP register (COPR) . . . . . . . . . . .68, 97

data direction register A (DDRA) . . . . .83

data direction register B (DDRB) . . . . .86

data direction register C (DDRC) . . . . .89

data direction register D (DDRD) . . . . .92

EPROM programming

input capture registers (ICRH/ICRL) . .103

input capture registers

(ICRH/L) . . . . . .110–111, 114, 116

mask option register

(MOR) . . . . . . . . . . .22, 37, 42, 96

output compare registers

(OCRH/L) . . . . . . . . . 110–111, 115

output compare registers

(OCRH/OCRL) . . . . . . . . . . . . . 104

port A data register (PORTA) . . . . . . . . 83

port B data register (PORTB) . . . . . . . . 85

port C data register (PORTC) . . . . . . . . 88

port D data register (PORTD) . . . . . . . . 91

SIOP control register

(SCR) . . . . . . . . . . . . . . . . . 121, 125, 127

SIOP data register (SDR) . . . . . . 126–127

SIOP status register (SSR) . . . . . . . . .126

timer control register (TCR) . . . . . 71, 109

timer registers (TRH/L) . . . . . . . . 110–112

timer status register

(TSR) . . . . . . . . . 71, 110, 114–115

ICF bit . . . . . . . . . . . . 71, 108, 111, 114, 116

ICIE bit . . . . . . . . . . . . . . . . . . . . 71, 108–109

IEDG bit . . . . . . . . . . . . . . . . . . . . . . . . . . 110

index register (X) . . . . . . . . . . . . . . . . . 49–53

input capture interrupt . . . . . . . . . . . . . . . 100

input capture registers

(ICRH/L) . . . . 103, 110–111, 114, 116

instruction set . . . . . . . . . . . . . . . . . . . . . . . 49

addressing modes . . . . . . . . . . . . . . . . 50

instruction set summary . . . . . . . . . . . . 58

instruction types . . . . . . . . . . . . . . . . . . 52

opcode map . . . . . . . . . . . . . . . . . . . . . 64

internal clock . . . . . . . . . . . . . . . . . . . . . . . 96

frequency . . . . . . . . . . . . . . . . . . . . . . . 27

internal RC oscillator . . . . . . . . 132, 134–135

Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 108

interrupts

external interrupt . . . . . . . . . . . . . . . . . . 69

external interrupt logic . . . . . . . . . . . . . 69

external interrupt timing . . . . . . . . . . . . 70

interrupt flowchart . . . . . . . . . . . . . . . . . 74

interrupt processing . . . . . . . . . . . . . . . 72

interrupt sources . . . . . . . . . . . . . . . . . . 68

interrupt stacking order . . . . . . . . . . . . . 72

reset/interrupt vector addresses . . . . . .73

Freescale Semiconductor, Inc.

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