| Electronic Components Datasheet Search |
|
FX980 Datasheet(PDF) 37 Page - CML Microcircuits |
|
|
|||||||||||||||||||||||||||||
FX980 Datasheet(HTML) 37 Page - CML Microcircuits |
|
37 / 86 page ![]() TETRA Baseband Processor FX980 © 1997 Consumer Microcircuits Limited 37 D/980/3 AuxDacData Title: Auxiliary DAC Data registers Address: (Eight registers) $0x18 to $0x1F Function: RW Description: There are two input registers for each of the four auxiliary DACs. Writing to the AuxDac#LsbData register writes the least significant two bits of DAC data. Writing to the AuxDac#MsbData register writes the most significant eight bits of DAC data and then passes all ten bits to the appropriate DAC input (only if the RamDacActive bit is set Low for DAC 1). If the AuxDac#MsbData register is written while the AuxDac#LsbData register is left constant, the converter may be treated as an 8-bit DAC. Bit Name Active State Function Address $0x18 7:2 RW Reserved. These bits should be set Low. Undefined on read. 1:0 AuxDac1LsbData Data RW Writing to this address writes the least significant two bits of the DacData1 register. These two bits may be read for test purposes. Address $0x19 7:0 AuxDac1MsbData Data RW Writing to this address writes the most significant eight bits of the DacData1 register and updates DAC 1. This register may also be read for test purposes. Address $0x1A 7:2 RW Reserved. These bits should be set Low. Undefined on read. 1:0 AuxDac2LsbData Data RW Writing to this address writes the least significant two bits of the DacData2 register. These two bits may be read for test purposes. Address $0x1B 7:0 AuxDac2MsbData Data RW Writing to this address writes the most significant eight bits of the DacData2 register and updates DAC 2. This register may also be read for test purposes. Address $0x1C 7:2 RW Reserved. These bits should be set Low. Undefined on read. 1:0 AuxDac3LsbData Data RW Writing to this address writes the least significant two bits of the DacData3 register. These two bits may be read for test purposes. Address $0x1D 7:0 AuxDac3MsbData Data RW Writing to this address writes the most significant eight bits of the DacData3 register and updates DAC 3. This register may also be read for test purposes. Address $0x1E 7:2 RW Reserved. These bits should be set Low. Undefined on read. 1:0 AuxDac4LsbData Data RW Writing to this address writes the least significant two bits of the DacData4 register. These two bits may be read for test purposes. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |