FX980 datasheet(78/86 Pages) CMLMICRO

78 / 86 page

TETRA Baseband Processor

FX980

D/980/3

Notes:

Offset adjustment for each channel is available by loading a 16-bit word into the receive offset register via the

serial interface.

Optimally, anti-alias filtering should be carried out as much as possible prior to any AGC function before the

receive inputs. This allows the AGC to act on a reduced bandwidth signal and thereby improve the relative

magnitude of the wanted part. The device has been designed to reduce the complexity of any external anti-

alias filter as much as possible and a 4-pole Butterworth with a -3dB point at about 60kHz should be adequate.

The internal anti-alias filter, if used, cannot provide the required 110dB attenuation at 2.3MHz and must be

supplemented by external filtering. The most simple supplementary system may be a one- or two-pole filter

before the AGC and an RC network after the AGC with a -3dB point on each filter of about 200kHz.

Auxiliary Circuit Parameters

Parameter

Typ

Units

Conditions/comments

DACs

Resolution

Settling time to 0.5 LSB

Output resistance

Integral non-linearity

Differential non-linearity

Zero error (offset)

Power (all DACs operating)

Minimum Resistive Load

RMS output noise voltage in 30kHz

bandwidth

ADC and Multiplexed inputs

Maximum input source impedance

Resolution

Maximum input signal "linear rate of

change" for < 1 bit error

Conversion time

Integral non-linearity

Differential non-linearity

Zero error (offset)

A-D Clock frequency

Input capacitance

Power

<10

<250

±20

<10

0.27

±20

MCLK/8

Bits

µSec

Ω

Bits

Bit

Ω

µV

Ω

Bits

mV/

µs

µSec

Bits

Bit

(Hz)

Worst case large signal

transition

Guaranteed Monotonic

Gives < 1 bit error

No missing codes

FX980 Datasheet(PDF) 78 Page - CML Microcircuits

FX980 Datasheet(HTML) 78 Page - CML Microcircuits

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