FX980 datasheet(79/86 Pages) CMLMICRO

79 / 86 page

TETRA Baseband Processor

FX980

D/980/3

1.7.1.

Electrical Performance

Timing Diagrams

The following timings are provisional:

1.7.1.1 Serial Ports

Timing Parameter

Marker

Min

Max

Units

MCLK to SClk out - low to high

cslh

MCLK to SClk out - high to low

cshl

CmdDat set-up to falling edge of SClk

sis

CmdFS set-up to falling edge of SClk

sis

CmdDat hold from fall edge of SClk

sih

CmdFS hold from fall edge of SClk

sih

RxDat propagation from rising edge of SClk

sop

RxFS propagation from rising edge of SClk

sop

CmdRdDat propagation from rising edge of SClk

sop

CmdRdFS propagation from rising edge of SClk

sop

RxDat hold from rising edge of SClk

soh

-5

RxFS hold from rising edge of SClk

soh

-5

CmdRdDat hold from rising edge of SClk

soh

-5

CmdRdFS hold from rising edge of SClk

soh

-5

**Cmd port in Bi-dir mode **

CmdDat propagation from rising edge of SClk

sop

CmdDat hold from rising edge of SClk

soh

-7

Figure 4 Serial Port Interfaces - Timing Parameters

FX980 Datasheet(PDF) 79 Page - CML Microcircuits

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