FX980 datasheet(4/86 Pages) CMLMICRO

4 / 86 page

TETRA Baseband Processor

FX980

D/980/3

1.3

Signal List

L6 Package

44 PLCC

Package

Signal

Description

Pin No.

Name

Type

MCLK

I/P

Master clock input (typically 9.216MHz)

SClk

O/P

Serial interface clock

CmdDat

Command serial interface Data

CmdFS

I/P

Command serial interface Frame

CmdRdDat

O/P

Command serial interface Read Data

CmdRdFS

O/P

Command serial interface Read Frame

RxDat

O/P

Receive serial interface Data

RxFS

O/P

Receive serial interface Strobe

N_IRQ

O/P

Interrupt request

N_RESET

I/P

Chip Reset

SCANSEL

I/P

Scan Select (normally tied low)

ITXP

O/P

Transmit "I" channel, positive output

ITXN

O/P

Transmit "I" channel, negative output

QTXP

O/P

Transmit "Q" channel, positive output

QTXN

O/P

Transmit "Q" channel, negative output

IRXP

I/P

Receive "I" channel, positive input

IRXN

I/P

Receive "I" channel, negative input

QRXP

I/P

Receive "Q" channel, positive input

QRXN

I/P

Receive "Q" channel, negative input

AUXADC1

I/P

Auxiliary ADC channel 1

AUXADC2

I/P

Auxiliary ADC channel 2

AUXADC3

I/P

Auxiliary ADC channel 3

AUXADC4

I/P

Auxiliary ADC channel 4

FX980 Datasheet(PDF) 4 Page - CML Microcircuits

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