FX980 datasheet(65/86 Pages) CMLMICRO

65 / 86 page

TETRA Baseband Processor

FX980

D/980/3

RxIQOffset

Title:

Receive I and Q Channel Offset correction register

Address:

$0x32, $0x33, $0x36, and $0x37 (4 locations)

Function:

Description:

This register controls the Rx Data path signal offset. This offset is a 2s-complement value

offset), which is applied to the Rx signal after the Gain Multiplier (Gval), but before the 63-tap and

49-tap FIR filters. The offset applied is at the discretion of the user. Inappropriate values may

cause arithmetic overflow in the subsequent operator sections. The result is given by the

formula:

D +

out

offset













Where:

Din

Dout

offset

is the signal input,

is the signal output,

is the 2s-complement value

in the register.

Bit

Name

Active State

Function

Address $0x32

7:0

RxIOffsetLSB

Data RW

Least significant 8 bits of the RxIOffset register (N

offset).

Address $0x33

7:4

Reserved. Set these bits Low. Undefined on read.

3:0

RxIOffsetMSB

Data RW

Most significant 4 bits of the RxIOffset register (N

offset).

Address $0x36

7:0

RxQOffsetLSB

Data RW

Least significant 8 bits of the RxQOffset register (N

offset).

Address $0x37

7:4

Reserved. Set these bits Low. Undefined on read.

3:0

RxQOffsetMSB

Data RW

Most significant 4 bits of the RxQOffset register (N

offset).

FX980 Datasheet(PDF) 65 Page - CML Microcircuits

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