FX980 datasheet(63/86 Pages) CMLMICRO

63 / 86 page

TETRA Baseband Processor

FX980

D/980/3

RxIQGainMult

Title:

Receive I and Q channel Gain Multiplier register

Address:

$0x30, $0x31, $0x34 and $0x35 (4 locations)

Function:

Description:

A 2s-complement multiplication is performed on the magnitude of the Rx Data path signal and

the result is then re-normalised to the system’s dynamic range: thus the function may be

considered as a digital attenuator. This multiplication is applied to the Rx signal after the ADC

decimation filter, but before offset adjustment and the 63-tap and 49-tap FIR filters. This register

sets the multiplier, the result being given by the formula:

out

val













Where:

Din

Dout

val

is the signal input,

is the signal output,

is the value in the register.

Bit

Name

Active State

Function

Address $0x30

7:0

RxIGainLSB

Data RW

Least significant 8 bits of the RxIGain register (G

val).

Address $0x31

7:3

Reserved. Set these bits Low. Undefined on read.

2:0

RxIGainMSB

Data RW

Most significant 3 bits of the RxIGain register (G

val).

Address $0x34

7:0

RxQGainLSB

Data RW

Least significant 8 bits of the RxQGain register (G

val).

Address $0x35

7:3

Reserved. Set these bits Low. Undefined on read.

2:0

RxQGainMSB

Data RW

Most significant 3 bits of the RxQGain register (G

val).

FX980 Datasheet(PDF) 63 Page - CML Microcircuits

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