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MPC5673F Datasheet(PDF) 121 Page - Freescale Semiconductor, Inc |
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MPC5673F Datasheet(HTML) 121 Page - Freescale Semiconductor, Inc |
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121 / 132 page  231 MDO12_GPIO231 –12 MDO12 Nexus message data out O F VDDE2 O/Low —/Down V1 AA1 Y5 A1 —— — A2 —— — G GPIO231 GPIO I/O 232 MDO13_GPIO232 –12 MDO13 Nexus message data out O F VDDE2 O/Low —/Down W2 AA2 AA1 A1 —— — A2 —— — G GPIO232 GPIO I/O 233 MDO14_GPIO233 –12 MDO14 Nexus message data out O F VDDE2 O/Low —/Down V3 AA3 AA2 A1 —— — A2 —— — G GPIO233 GPIO I/O 234 MDO15_GPIO234 –12 MDO15 Nexus message data out O F VDDE2 O/Low —/Down U4 Y4 AA3 A1 —— — A2 —— — G GPIO234 GPIO I/O 224 MSEO0 –12 MSEO0 Nexus message start/end out O F VDDE2 O/Low MSEO/HI P2 U2 U6 225 MSEO1 –12 MSEO1 Nexus message start/end out O F VDDE2 O/Low MSEO/HI N3T3U5 226 RDY –12 RDY Nexus ready output O F VDDE2 O/Low RDY/HI M4 R4 U3 —TCK –12 TCK JTAG test clock input I F VDDE2 TCK/Down TCK/Down Y1 AB2 AB2 —TDI –12 TDI JTAG test data input I F VDDE2 TDI/Up TDI/Up Y2 AC2 AC2 228 TDO –12 TDO JTAG test data output O F VDDE2 TDO/Up TDO/Up W1 AB1 AB1 —TMS –12 TMS JTAG test mode select input I F VDDE2 TMS/Up TMS/Up W3 AB3 AB3 —JCOMP –12 JCOMP JTAG TAP controller enable I F VDDE2 JCOMP/Down JCOMP/Down M1 R1 U2 — TEST — TEST Test mode select (not for customer use) IF VDDEH1 TEST/Down TEST/Down B4 B4 B4 — VDDSYN — VDDSYN Clock synthesizer power input I VDDE VDDSYN VDDSYN VDDSYN Y22 AD26 AD26 Table 43. Signal Properties and Muxing Summary (continued) Signal Name2 Function4 Function Summary State during RESET7 State after RESET8 Package Location |
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