MPC5673F datasheet(122/132 Pages) FREESCALE

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—

VSSSYN

—

VSSSYN

Clock synthesizer ground input

VSSE

VDDSYN

VSSSYN

U22

AA26

—VSTBY

—

VSTBY

SRAM standby power input

VHV

VDDEH1

VSTBY

—

REGSEL

—

REGSEL

Selects regulator mode (Linear/Switch

mode)

IAE

VDDREG

REGSEL

V20

W23

—REGCTL

—

REGCTL

Regulator controller output to

base/gate of power transistor

VDDREG

REGCTL

T22

Y26

—VSSFL

—

VSSFL

Tie to VSS

VSS

VDDREG

VSSFL

V21

AB25

—

VDDREG

—

VDDREG

Source voltage for on-chip regulators

and Low voltage detect circuits

VDDINT

VDDREG

U21

AA25

1 The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number in pins that have GPIO functionality. For pins that do not have GPIO

functionality, this number is the PCR number.

2 The primary signal name is used as the pin label on the BGA map for identification purposes. However, the primary signal function is not available on all devices and is

indicated by a dash in the following table columns: Signal Functions, P/F/G, and I/O Type.

3 P/A/G stands for Primary/Alternate/GPIO . This column indicates which function on a pin is Primary, Alternate 1, Alternate 2, (Alternate n) and GPIO.

4 Each line in the Function column corresponds to a separate signal function on the pin. For all device I/O pins, the primary, alternate, or GPIO signal functions are

designated in the PA field of the SIU_PCRn registers except where explicitly noted.

5 MH = High voltage, medium speed

F = Fast speed

FS = Fast speed with slew

AE = Analog with ESD protection circuitry (up/down = pull up and pull down circuits included in the pad)

VHV = Very high voltage

6 VDDE (fast I/O) and VDDEH (slow I/O) power supply inputs are grouped into segments. Each segment of VDDEH pins can connect to a separate 3.3–5.0 V (+5%/–10%)

power supply input. Each segment of VDDE pins can connect to a separate 3.3 V (±10%) power supply.

7 The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. The terminology used in this column

is: O – output, I – input, Up – weak pull up enabled, Down – weak pulldown enabled, Low – output driven low, High – output driven high, ABS — Auto Baud Select (during

Reset or until JCOMP assertion). A dash on the left side of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the

slash denotes that there is no weak pull up/down enabled on the pin. The signal name to the left or right of the slash indicates the pin is enabled.

8 The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the pin are

off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin.

9 This signal name includes eTPU_C functionality that this device does not have. This is for forward compatibility with devices that have an eTPU_C.

10 NMI does not have a PCR PA configuration; it is enabled when NMI is enabled through the SIU_IREER and SIU_IFEER registers.

11 Nexus reset is different than system reset; MDO 1-11 are enabled when trace (RPM or FPM) is enabled, and MDO 12-15 when FPM trace is enabled. MSEO and MCKO

are also dependent on trace (RPM or FPM) being enabled.

Table 43. Signal Properties and Muxing Summary (continued)

Signal Name2

Function4

Function Summary

State during

RESET7

State

after RESET8

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MPC5673F Datasheet(PDF) 122 Page - Freescale Semiconductor, Inc

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