R5F562T7DDFM datasheet(10/94 Pages) RENESAS

10 / 94 page

R01DS0096EJ0100 Rev.1.00

Page 10 of 92

Apr 20, 2011

RX62T Group

1. Overview

1.3

Block Diagram

Figure 1.2 shows a block diagram.

Figure 1.2

Block Diagram

ROM

RAM

RX CPU

DTC

POR

ICU

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port B

Port D

Port E

Clock

generation

circuit

RIIC

10-bit A/D converter

 12 channels

RSPI

IWDT

SCI

 3 channels

MTU3

Port G

CRC

CAN (as an optional function)

POE3

CMT

 2 channels (unit 0)

LIN

Notes:

1. The installation of the 10-bit A/D converter and ports 1 to G is different depending on the package.

2. For details on the internal peripheral bus configuration, see section 12, Buses in the User's Manual: Hardware.

12-bit A/D converter

 4 channels (unit 0)

Programmable gain amps

 3 channels

Sample-and-hold circuits

for the pin section

 3 channels

Window comparator

 3 channels

WDT

Data flash

LVD

CAN: CAN module

LIN:

LIN module

RSPI: Renesas serial peripheral interface

LVD: Voltage detection circuit

ICU:

Interrupt control unit

WDT: Watchdog timer

IWDT: Independent watchdog timer

CRC: CRC (cyclic redundancy check) calculator

[Legend]

POR:

Power-on reset circuit

DTC:

Data transfer controller

MTU3: Multi-function timer pulse unit 3

POE3: Port output enable 3

GPT:

General PWM timer

CMT:

Compare match timer

SCI:

Serial communications interface

RIIC:

2C bus interface

GPT

12-bit A/D converter

 4 channels (unit 1)

Programmable gain amps

 3 channels

Sample-and-hold circuits

for the pin section

 3 channels

Window comparator

 3 channels

CMT

 2 channels (unit 1)

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