ST10F280_12 datasheet(174/239 Pages) STMICROELECTRONICS

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System reset

ST10F280

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Doc ID 8673 Rev. 3

Figure 67.

Synchronous warm reset (long low pulse on RSTIN)

RSTIN rising edge to internal latch of PORT0 is 3 CPU (6 TCL) clock cycles if the PLL is bypassed and the

prescaler is on (fCPU = fXTAL / 2), else it is 4 CPU clock cycles (8 TCL).

If during the reset condition (RSTIN low), VRPD voltage drops below the threshold voltage (about 2.5V for

5V operation), the asynchronous reset is then immediately entered.

RSTIN pin is pulled low if bit BDRSTEN (bit 5 of SYSCON register) was previously set by soft-ware. Bit

BDRSTEN is cleared after reset.

17.3

Software reset

The reset sequence can be triggered at any time using the protected instruction SRST

(software reset). This instruction can be executed deliberately within a program, for example

to leave bootstrap loader mode, or upon a hardware trap that reveals a system failure.

Upon execution of the SRST instruction, the internal reset sequence (1024 TCL) is started.

The microcontroller behaviour is the same as for a Short Hardware reset, except that only

P0.12...P0.6 bit are latched at the end of the reset sequence, while P0.5...P0.2 bit are

cleared.

17.4

Watchdog timer reset

When the watchdog timer is not disabled during the initialization or when it is not regularly

serviced during program execution it will overflow and it will trigger the reset sequence.

Unlike hardware and software resets, the watchdog reset completes a running external bus

cycle if this bus cycle either does not use READY, or if READY is sampled active (low) after

the programmed wait states. When READY is sampled inactive (high) after the programmed

wait states the running external bus cycle is aborted. Then the internal reset sequence is

started. At the end of the internal reset sequence (1024 TCL), only P0.12...P0.6 bit are

latched, while previously latched values of P0.5...P0.2 are cleared.

ST10F280 Datasheet(PDF) 174 Page - STMicroelectronics