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ST10F280 Datasheet(PDF) 171 Page - STMicroelectronics |
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ST10F280 Datasheet(HTML) 171 Page - STMicroelectronics |
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171 / 239 page ![]() ST10F280 System reset Doc ID 8673 Rev. 3 171/239 17 System reset System reset initializes the MCU in a predefined state. There are five ways to activate a reset state. The system start-up configuration is different for each case as shown in Table 35. 17.1 Asynchronous reset (long hardware reset) An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low level. Then the MCU is immediately forced in reset default state. It pulls low RSTOUT pin, it cancels pending internal hold states if any, it waits for any internal access cycles to finish, it aborts external bus cycle, it switches buses (data, address and control signals) and I/O pin drivers to high-impedance, it pulls high PORT0 pins and the reset sequence starts. 17.1.1 Power-on reset The asynchronous reset must be used during the power-on of the MCU. Depending on crystal frequency, the on-chip oscillator needs about 10ms to 50ms to stabilize. The logic of the MCU does not need a stabilized clock signal to detect an asynchronous reset, so it is suitable for power-on conditions. To ensure a proper reset sequence, the RSTIN pin and the RPD pin must be held at low level until the MCU clock signal is stabilized and the system configuration value on PORT0 is settled. 17.1.2 Hardware reset The asynchronous reset must be used to recover from catastrophic situations of the application. It may be triggerred by the hardware of the application. Internal hardware logic and application circuitry are described in Reset circuitry chapter and Figure 68, Figure 69 and Figure 66. 17.1.3 Exit of asynchronous reset state When the RSTIN pin is pulled high, the MCU restarts. The system configuration is latched from PORT0 and ALE, RD and R/W pins are driven to their inactive level. The MCU starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine. Timing of asynchronous reset sequence are summarized in Figure 61. Table 35. Reset event definition Reset source Short-cut Conditions Power-on reset PONR Power-on Long Hardware reset (synchronous & asynchronous) LHWR t RSTIN > 1032 TCL Short Hardware reset (synchronous reset) SHWR 4 TCL < t RSTIN < 1032 TCL Watchdog Timer reset WDTR WDT overflow Software reset SWR SRST execution |
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