ST10F280_12 datasheet(172/239 Pages) STMICROELECTRONICS

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System reset

ST10F280

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Doc ID 8673 Rev. 3

Figure 65.

Asynchronous reset timing

Note:

1. RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is

bypassed and the prescaler is on (fCPU =fXTAL / 2), else it is 4 CPU clock cycles (8 TCL) .

17.2

Synchronous reset (warm reset)

A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high

level. In order to properly activate the internal reset logic of the MCU, the RSTIN pin must be

held low, at least, during 4 TCL (2 periods of CPU clock). The I/O pins are set to high

impedance and RSTOUT pin is driven low. After RSTIN level is detected, a short duration of

12 TCL (approximately 6 periods of CPU clock) elapes, during which pending internal hold

states are cancelled and the current internal access cycle if any is completed. External bus

cycle is aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of

SYSCON register was previously set by software. This bit is always cleared on power-on or

after a reset sequence.

17.2.1

Exit of synchronous reset state

The internal reset sequence starts for 1024 TCL (512 periods of CPU clock) and RSTIN pin

level is sampled. The reset sequence is extended until RSTIN level becomes high. Then, the

MCU restarts. The system configuration is latched from PORT0 and ALE, RD and R/W pins

are driven to their inactive level. The MCU starts program execution from memory location

00'0000h in code segment 0. This starting location will typically point to the general

initialization routine. Timing of synchronous reset sequence are summarized in Figure 66

and Figure 67.

ST10F280 Datasheet(PDF) 172 Page - STMicroelectronics