WM8961GEFLSLASHV datasheet(65/116 Pages) WOLFSON

65 / 116 page

WM8961

Pre-Production

PP, August 2009, Rev 3.1

ADC-DAC LOOPBACK

Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data from

the ADC audio interface is fed directly into the DAC data input..

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Audio

Interface

LOOPBACK

Digital Loopback Function

0 = No loopback.

1 = Loopback enabled, ADC data output

is fed directly into DAC data input.

Table 48 Loopback Control

CONTROL WRITE SEQUENCER

The write sequencer allows register write sequences to be stored in an area of memory on the device

and then triggered by another register write. In this way complex sequences of writes can be used to

configure the device without the need for constant intervention by the main processor. This aids pop

and click suppression and simplifies power-on and power-off sequences.

MCLK must be applied to the WM8961 while making use of the write sequencer.

The control write sequencer contains 2 memories. It contains a RAM (locations 0 to 31) and a ROM

(locations 32 to 48). A number of pre-defined sequences are stored within both these areas of

memory. This enables the most popular configurations to be selected via a single command. It also

allows deployment of factory proven ‘patches’ into the field. The pre-defined sequences within the

RAM can be overwritten by the user. This is done by loading new sequences via the control interface

logic shown in Figure 40.

The control interface logic provides connectivity to the control interface and access to the control

registers. In WM8961, a multiplexer has been added to allow switch over, such that the control write

sequencer is connected to the registers instead.

Figure 40 Location of the Control Sequencer in the Control Path

The sequencer allows the controlling processor to initiate a sequence of commands. The delays

between each command in the sequence are controlled on-chip – and are not affected by activities

elsewhere in the system. Once a sequence is initiated, the processor is then free to concentrate on

other parts of the system. A status register is provided to allow the processor to check that one

sequence is complete before starting another.

Although pop and click suppression is the most obvious application, there are other applications. Any

sequence of control writes can be automated, enabling the processor to initiate a thread of

asynchronous control events before performing other tasks or going into a power down mode.

WM8961GEFL/V Datasheet(PDF) 65 Page - Wolfson Microelectronics plc

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