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WM8961GEFL/V Datasheet(PDF) 89 Page - Wolfson Microelectronics plc |
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WM8961GEFL/V Datasheet(HTML) 89 Page - Wolfson Microelectronics plc |
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89 / 116 page ![]() WM8961 Pre-Production w PP, August 2009, Rev 3.1 89 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R17 (11h) ALC1 8:7 ALCSEL[1:0] 00 ALC Function Select 00 : ALC off (PGA gain set by register) 01 : Right channel only 10: Left channel only 11 : Stereo (PGA registers unused). Note: ensure that LINVOL and RINVOL settings are the same before entering this mode. 6:4 MAXGAIN[2:0] 111 ALC Max Gain 000 : -18dB 001 : -12dB 010 : -6dB 011 : 0dB 100 : 6dB 101 : 12dB 110 : 18dB 111 : 24dB 3:0 ALCL[3:0] 1011 ALC Target Level (dB FS) 0000 : -28.5 0001 : -27 …1.5dB steps… 1111 : -6 Register 11h ALC1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R18 (12h) ALC2 6:4 MINGAIN[2:0] 000 Min gain setting 000 : -23.25dB 001 : -17.25dB 010 : -11.25dB 011 : -5.25dB 100 : +0.75dB 101 : +6.75dB 110 : +12.75dB 111 : +18.75dB 3:0 HLD[3:0] 0000 ALC Hold time 0000 : 0ms 0001 : 2.67ms 0010 : 5.33ms Doubling with each step up to… 1111 : 43.691s Register 12h ALC2 |
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